diff mbox series

[PULL,20/54] cpus: Fix style in cpu-target.c

Message ID 20250306154737.70886-21-philmd@linaro.org
State Accepted
Commit c90476325cf669d9bba15f4fd8d8637926f272a2
Headers show
Series [PULL,01/54] qemu/compiler: Absorb 'clang-tsa.h' | expand

Commit Message

Philippe Mathieu-Daudé March 6, 2025, 3:47 p.m. UTC 
Fix style on code we are going to modify.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250123234415.59850-16-philmd@linaro.org>
---
 cpu-target.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/cpu-target.c b/cpu-target.c
index 83688f1d508..b925b9391e8 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -48,12 +48,15 @@  static int cpu_common_post_load(void *opaque, int version_id)
 {
     CPUState *cpu = opaque;
 
-    /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
-       version_id is increased. */
+    /*
+     * 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
+     * version_id is increased.
+     */
     cpu->interrupt_request &= ~0x01;
     tlb_flush(cpu);
 
-    /* loadvm has just updated the content of RAM, bypassing the
+    /*
+     * loadvm has just updated the content of RAM, bypassing the
      * usual mechanisms that ensure we flush TBs for writes to
      * memory we've translated code from. So we must flush all TBs,
      * which will now be stale.