| Message ID | 20250306163925.2940297-11-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [01/10] target/arm: Move A32_BANKED_REG_{GET, SET} macros to cpregs.h | expand |
On 3/6/25 08:39, Peter Maydell wrote: > In the Arm ARM, rule R_TYTWB states that returning to AArch32 > is an illegal exception return if: > * AArch32 is not supported at any exception level > * the target EL is configured for AArch64 via SCR_EL3.RW > or HCR_EL2.RW or via CPU state at reset > > We check the second of these, but not the first (which can only be > relevant for the case of a return to EL0, because if AArch32 is not > supported at one of the higher ELs then the RW bits will have an > effective value of 1 and the the "configured for AArch64" condition > will hold also). > > Add the missing condition. This isn't currently a bug because > all our CPUs support AArch32 at EL0, but future CPUs we add > might be 64-bit only. > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > target/arm/tcg/helper-a64.c | 5 +++++ > 1 file changed, 5 insertions(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index e2bdf07833d..9244848efed 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -678,6 +678,11 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) goto illegal_return; } + if (!return_to_aa64 && !cpu_isar_feature(aa64_aa32, cpu)) { + /* Return to AArch32 when CPU is AArch64-only */ + goto illegal_return; + } + if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; }
In the Arm ARM, rule R_TYTWB states that returning to AArch32 is an illegal exception return if: * AArch32 is not supported at any exception level * the target EL is configured for AArch64 via SCR_EL3.RW or HCR_EL2.RW or via CPU state at reset We check the second of these, but not the first (which can only be relevant for the case of a return to EL0, because if AArch32 is not supported at one of the higher ELs then the RW bits will have an effective value of 1 and the the "configured for AArch64" condition will hold also). Add the missing condition. This isn't currently a bug because all our CPUs support AArch32 at EL0, but future CPUs we add might be 64-bit only. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/helper-a64.c | 5 +++++ 1 file changed, 5 insertions(+)