| Message ID | 20250306-topic-dt_bindings_fixups-v1-2-0c84aceb0ef9@oss.qualcomm.com |
|---|---|
| State | New |
| Headers | show |
| Series | Various dt-bindings fixes | expand |
On Thu, Mar 06, 2025 at 07:11:14PM +0100, Konrad Dybcio wrote: > From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > > There's a separate path that allows register access from CPUSS. > Describe it. > > Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > --- > Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml index 163fc83c1e80cf07383f9aef510f2f58a26e1ecc..3733d8cd2ae07597952ebdc1d74edda330173ef6 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml @@ -38,12 +38,16 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from the MDP0 port to the data bus + - description: Interconnect path from the MDP1 port to the data bus + - description: Interconnect path from the CPU to the reg bus interconnect-names: items: - const: mdp0-mem - const: mdp1-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$":