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From: Jie Gan <quic_jiegan@quicinc.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
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Subject: [PATCH v1 4/4] arm64: dts: qcom: sa8775p: Add interrupts to CTCU
device
Date: Mon, 10 Mar 2025 17:04:07 +0800
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diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 93ca37843990..091ae73774fa 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2425,6 +2425,11 @@ ctcu@4001000 { clocks = <&aoss_qmp>; clock-names = "apb"; + interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "etr0", + "etr1"; + in-ports { #address-cells = <1>; #size-cells = <0>;
Add interrupts to enable byte-cntr function for TMC ETR devices. Signed-off-by: Jie Gan <quic_jiegan@quicinc.com> --- Dependency: prerequisite-message-id: 20250303032931.2500935-11-quic_jiegan@quicinc.com --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++ 1 file changed, 5 insertions(+)