similarity index 59%
rename from Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml
rename to Documentation/devicetree/bindings/phy/snps,eusb2-phy.yaml
@@ -1,16 +1,16 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#
+$id: http://devicetree.org/schemas/phy/snps,eusb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm SNPS eUSB2 phy controller
+title: SNPS eUSB2 phy controller
maintainers:
- Abel Vesa <abel.vesa@linaro.org>
description:
- eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
+ eUSB2 controller supports LS/FS/HS usb connectivity.
properties:
compatible:
@@ -23,6 +23,7 @@ properties:
- qcom,x1e80100-snps-eusb2-phy
- const: qcom,sm8550-snps-eusb2-phy
- const: qcom,sm8550-snps-eusb2-phy
+ - const: samsung,exynos2200-snps-eusb2-phy
reg:
maxItems: 1
@@ -31,12 +32,12 @@ properties:
const: 0
clocks:
- items:
- - description: ref
+ minItems: 1
+ maxItems: 3
clock-names:
- items:
- - const: ref
+ minItems: 1
+ maxItems: 3
resets:
maxItems: 1
@@ -62,7 +63,52 @@ required:
- clock-names
- vdd-supply
- vdda12-supply
- - resets
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8550-snps-eusb2-phy
+
+ then:
+ properties:
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: ref
+
+ clock-names:
+ items:
+ - const: ref
+
+ required:
+ - resets
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos2200-snps-eusb2-phy
+
+ then:
+ properties:
+
+ clocks:
+ items:
+ - description: Reference clock
+ - description: Bus (APB) clock
+ - description: Control clock
+
+ clock-names:
+ items:
+ - const: ref
+ - const: bus
+ - const: ctrl
additionalProperties: false
As Samsung has been using the same Synopsys eUSB2 IP in Exynos2200, albeit with a different register layout, rename qcom,snps-eusb2-phy to snps,eusb2-phy and drop mentions of it being only for Qualcomm SoCs in the binding description. Document the exynos2200 eUSB2 compatible. Unlike the currently documented Qualcomm SoCs, it doesn't provide reset lines for reset control and uses more clocks. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- ...nps-eusb2-phy.yaml => snps,eusb2-phy.yaml} | 62 ++++++++++++++++--- 1 file changed, 54 insertions(+), 8 deletions(-) rename Documentation/devicetree/bindings/phy/{qcom,snps-eusb2-phy.yaml => snps,eusb2-phy.yaml} (59%)