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From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>,
Brian Cain <brian.cain@oss.qualcomm.com>, =?utf-8?q?Philippe_Mathieu-Daud?=
=?utf-8?q?=C3=A9?= <philmd@linaro.org>
Subject: [PATCH-for-10.1 v4 04/16] target/hexagon: Add memory order definition
Date: Sat, 5 Apr 2025 18:13:08 +0200
Message-ID: <20250405161320.76854-5-philmd@linaro.org>
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tcg: philmd's queue
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expand
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diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 635d509e743..22bffa78816 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -25,4 +25,9 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 +/* + * Hexagon processors have a strong memory model. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL) + #endif