| Message ID | 20250405105529.309711-1-mitltlatltl@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: qcom: sm8650: add the missing l2 cache node | expand |
On 05/04/2025 12:55, Pengyu Luo wrote: > Only two little a520s share the same L2, every a720 has their own L2 > cache. > > Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") > Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index a2b3d97ab..f47f29ec8 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -187,7 +187,7 @@ cpu3: cpu@300 { > power-domain-names = "psci"; > > enable-method = "psci"; > - next-level-cache = <&l2_200>; > + next-level-cache = <&l2_300>; > capacity-dmips-mhz = <1792>; > dynamic-power-coefficient = <238>; > > @@ -203,6 +203,13 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, > &epss_l3 SLAVE_EPSS_L3_SHARED>; > > #cooling-cells = <2>; > + > + l2_300: l2-cache { > + compatible = "cache"; > + cache-level = <2>; > + cache-unified; > + next-level-cache = <&l3_0>; > + }; > }; > > cpu4: cpu@400 { Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index a2b3d97ab..f47f29ec8 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -187,7 +187,7 @@ cpu3: cpu@300 { power-domain-names = "psci"; enable-method = "psci"; - next-level-cache = <&l2_200>; + next-level-cache = <&l2_300>; capacity-dmips-mhz = <1792>; dynamic-power-coefficient = <238>; @@ -203,6 +203,13 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, &epss_l3 SLAVE_EPSS_L3_SHARED>; #cooling-cells = <2>; + + l2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu4: cpu@400 {
Only two little a520s share the same L2, every a720 has their own L2 cache. Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)