| Message ID | 354ecd628fdd292d2125570a6b10a93cbecb7706.1744666011.git.Ryan.Wanner@microchip.com |
|---|---|
| State | New |
| Headers | show |
| Series | Enable Power Modes Support for SAMA7D65 SoC | expand |
Hi, Ryan, On 15.04.2025 00:41, Ryan.Wanner@microchip.com wrote: > From: Ryan Wanner <Ryan.Wanner@microchip.com> > > Add SRAM, secumod, UDDRC, and DDR3phy to enable support for low power modes. > > Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> > --- > arch/arm/boot/dts/microchip/sama7d65.dtsi | 35 +++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi > index b6710ccd4c36..8439c6a9e9f2 100644 > --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi > +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi > @@ -47,6 +47,14 @@ slow_xtal: clock-slowxtal { > }; > }; > > + ns_sram: sram@100000 { > + compatible = "mmio-sram"; > + reg = <0x100000 0x20000>; > + ranges; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > + > soc { > compatible = "simple-bus"; > ranges; > @@ -58,6 +66,23 @@ sfrbu: sfr@e0008000 { > reg = <0xe0008000 0x20>; > }; > > + securam: sram@e0000800 { > + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; > + reg = <0xe0000800 0x4000>; > + ranges = <0 0xe0000800 0x4000>; > + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; > + #address-cells = <1>; > + #size-cells = <1>; > + no-memory-wc; > + }; > + > + secumod: security-module@e0004000 { > + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; > + reg = <0xe0004000 0x4000>; > + gpio-controller; > + #gpio-cells = <2>; > + }; > + These should have be before sfrbu for keeping nodes soted by their address. I'll adjust while applying. Thank you, Claudiu
diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index b6710ccd4c36..8439c6a9e9f2 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -47,6 +47,14 @@ slow_xtal: clock-slowxtal { }; }; + ns_sram: sram@100000 { + compatible = "mmio-sram"; + reg = <0x100000 0x20000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + }; + soc { compatible = "simple-bus"; ranges; @@ -58,6 +66,23 @@ sfrbu: sfr@e0008000 { reg = <0xe0008000 0x20>; }; + securam: sram@e0000800 { + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; + reg = <0xe0000800 0x4000>; + ranges = <0 0xe0000800 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; + #address-cells = <1>; + #size-cells = <1>; + no-memory-wc; + }; + + secumod: security-module@e0004000 { + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; + reg = <0xe0004000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + }; + pioa: pinctrl@e0014000 { compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; @@ -227,6 +252,16 @@ i2c10: i2c@600 { }; }; + uddrc: uddrc@e3800000 { + compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; + reg = <0xe3800000 0x4000>; + }; + + ddr3phy: ddr3phy@e3804000 { + compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; + reg = <0xe3804000 0x1000>; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; reg = <0xe8c11000 0x1000>,