| Message ID | 20250425-sm6350-gdsc-val-v1-4-1f252d9c5e4e@fairphone.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/4] clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs | expand |
On 4/25/2025 5:42 PM, Luca Weiss wrote: > Compared to the msm-4.19 driver the mainline GDSC driver always sets the > bits for en_rest, en_few & clk_dis, and if those values are not set > per-GDSC in the respective driver then the default value from the GDSC > driver is used. The downstream driver only conditionally sets > clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree. > > Correct this situation by explicitly setting those values. For all GDSCs > the reset value of those bits are used, with the exception of > gpu_cx_gdsc which has an explicit value (qcom,clk-dis-wait-val = <8>). > > Fixes: 013804a727a0 ("clk: qcom: Add GPU clock controller driver for SM6350") > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- > drivers/clk/qcom/gpucc-sm6350.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c > index 35ed0500bc59319f9659aef81031b34d29fc06a4..ee89c42413f885f21f1470b1f7887d052e52a75e 100644 > --- a/drivers/clk/qcom/gpucc-sm6350.c > +++ b/drivers/clk/qcom/gpucc-sm6350.c > @@ -413,6 +413,9 @@ static struct clk_branch gpu_cc_gx_vsense_clk = { > static struct gdsc gpu_cx_gdsc = { > .gdscr = 0x106c, > .gds_hw_ctrl = 0x1540, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0x8, > .pd = { > .name = "gpu_cx_gdsc", > }, > @@ -423,6 +426,9 @@ static struct gdsc gpu_cx_gdsc = { > static struct gdsc gpu_gx_gdsc = { > .gdscr = 0x100c, > .clamp_io_ctrl = 0x1508, > + .en_rest_wait_val = 0x2, > + .en_few_wait_val = 0x2, > + .clk_dis_wait_val = 0x2, > .pd = { > .name = "gpu_gx_gdsc", > .power_on = gdsc_gx_do_nothing_enable, > Reviewed-by: Taniya Das <quic_tdas@quicinc.com>
diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c index 35ed0500bc59319f9659aef81031b34d29fc06a4..ee89c42413f885f21f1470b1f7887d052e52a75e 100644 --- a/drivers/clk/qcom/gpucc-sm6350.c +++ b/drivers/clk/qcom/gpucc-sm6350.c @@ -413,6 +413,9 @@ static struct clk_branch gpu_cc_gx_vsense_clk = { static struct gdsc gpu_cx_gdsc = { .gdscr = 0x106c, .gds_hw_ctrl = 0x1540, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x8, .pd = { .name = "gpu_cx_gdsc", }, @@ -423,6 +426,9 @@ static struct gdsc gpu_cx_gdsc = { static struct gdsc gpu_gx_gdsc = { .gdscr = 0x100c, .clamp_io_ctrl = 0x1508, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0x2, .pd = { .name = "gpu_gx_gdsc", .power_on = gdsc_gx_do_nothing_enable,
Compared to the msm-4.19 driver the mainline GDSC driver always sets the bits for en_rest, en_few & clk_dis, and if those values are not set per-GDSC in the respective driver then the default value from the GDSC driver is used. The downstream driver only conditionally sets clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree. Correct this situation by explicitly setting those values. For all GDSCs the reset value of those bits are used, with the exception of gpu_cx_gdsc which has an explicit value (qcom,clk-dis-wait-val = <8>). Fixes: 013804a727a0 ("clk: qcom: Add GPU clock controller driver for SM6350") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> --- drivers/clk/qcom/gpucc-sm6350.c | 6 ++++++ 1 file changed, 6 insertions(+)