| Message ID | 20250426-b4-media-committers-25-04-25-camss-supplies-v3-1-19e5e72ffc3e@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | media: qcom: camss: x1e80100: Add support for individual CSIPHY supplies | expand |
On Sat, Apr 26, 2025 at 11:52:48PM GMT, Bryan O'Donoghue wrote: > Declare a CSIPHY regulator pair 0p8 and 1p2 for each CSIPHY. > > Name the inputs based on the voltage so as to have a consistent naming of > these rails across SoCs and PCBs. > > There are no upstream users of this yaml definition yet so this change is > safe to make. > > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > --- > .../bindings/media/qcom,x1e80100-camss.yaml | 52 +++++++++++++++++----- > 1 file changed, 40 insertions(+), 12 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml > index 113565cf2a991a8dcbc20889090e177e8bcadaac..dc7c1a9394c3b547f5e0885bf501ed42dfbeba88 100644 > --- a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml > +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml > @@ -118,14 +118,6 @@ properties: > - const: ife1 > - const: top > > - vdd-csiphy-0p8-supply: > - description: > - Phandle to a 0.8V regulator supply to a PHY. > - > - vdd-csiphy-1p2-supply: > - description: > - Phandle to 1.8V regulator supply to a PHY. > - > ports: > $ref: /schemas/graph.yaml#/properties/ports > > @@ -157,6 +149,30 @@ properties: > - clock-lanes > - data-lanes > > + vdd-csiphy0-0p8-supply: > + description: Phandle to a 0.8V regulator supply to csiphy0. > + > + vdd-csiphy0-1p2-supply: > + description: Phandle to a 1.2V regulator supply to csiphy0. Block has VDD_A_CSI_0_1_1P2 input, not separate one for CSI0 and CS1. I don't get what is the benefit of this and commit msg does not help me to understand such choice. On IRC I clarified you could have less supplies in the binding than number of actual pins, to make things simpler and more consistent, but you did here reverse: more supplies which do not exist. Best regards, Krzysztof
On 28/04/2025 08:14, Krzysztof Kozlowski wrote: > Block has VDD_A_CSI_0_1_1P2 input, not separate one for CSI0 and CS1. > I don't get what is the benefit of this and commit msg does not help me > to understand such choice. > > On IRC I clarified you could have less supplies in the binding than > number of actual pins, to make things simpler and more consistent, but > you did here reverse: more supplies which do not exist. So the idea here is to make a consistent - csiphy#-voltage-XpY Which means that each PHY will have voltage rail names like vdd-csiphy0-0p8 vdd-csiphy0-1p2 vdd-csiphy0-1p8 Irrespective of the SoC pin name. The motivation for that is to have the names be consistent across SoCs which is I believe what we have discussed should be the case. That means that each phy will have its own named set of voltage rails, consistently named across SoCs even if the pin-name is shared by the PHYs on the SoC pinout. Is that not the namespace consistency you've been looking for ? --- bod
diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml index 113565cf2a991a8dcbc20889090e177e8bcadaac..dc7c1a9394c3b547f5e0885bf501ed42dfbeba88 100644 --- a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -118,14 +118,6 @@ properties: - const: ife1 - const: top - vdd-csiphy-0p8-supply: - description: - Phandle to a 0.8V regulator supply to a PHY. - - vdd-csiphy-1p2-supply: - description: - Phandle to 1.8V regulator supply to a PHY. - ports: $ref: /schemas/graph.yaml#/properties/ports @@ -157,6 +149,30 @@ properties: - clock-lanes - data-lanes + vdd-csiphy0-0p8-supply: + description: Phandle to a 0.8V regulator supply to csiphy0. + + vdd-csiphy0-1p2-supply: + description: Phandle to a 1.2V regulator supply to csiphy0. + + vdd-csiphy1-0p8-supply: + description: Phandle to a 0.8V regulator supply to csiphy1. + + vdd-csiphy1-1p2-supply: + description: Phandle to a 1.2V regulator supply to csiphy1. + + vdd-csiphy2-0p8-supply: + description: Phandle to a 0.8V regulator supply to csiphy2. + + vdd-csiphy2-1p2-supply: + description: Phandle to a 1.2V regulator supply to csiphy2. + + vdd-csiphy4-0p8-supply: + description: Phandle to a 0.8V regulator supply to csiphy4. + + vdd-csiphy4-1p2-supply: + description: Phandle to a 1.2V regulator supply to csiphy4. + required: - compatible - reg @@ -170,10 +186,22 @@ required: - iommus - power-domains - power-domain-names - - vdd-csiphy-0p8-supply - - vdd-csiphy-1p2-supply - ports +anyOf: + - required: + - vdd-csiphy0-0p8-supply + - vdd-csiphy0-1p2-supply + - required: + - vdd-csiphy1-0p8-supply + - vdd-csiphy1-1p2-supply + - required: + - vdd-csiphy2-0p8-supply + - vdd-csiphy2-1p2-supply + - required: + - vdd-csiphy4-0p8-supply + - vdd-csiphy4-1p2-supply + additionalProperties: false examples: @@ -347,8 +375,8 @@ examples: "ife1", "top"; - vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>; - vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>; + vdd-csiphy0-0p8-supply = <&csiphy_0p8_supply>; + vdd-csiphy0-1p2-supply = <&csiphy_1p2_supply>; ports { #address-cells = <1>;
Declare a CSIPHY regulator pair 0p8 and 1p2 for each CSIPHY. Name the inputs based on the voltage so as to have a consistent naming of these rails across SoCs and PCBs. There are no upstream users of this yaml definition yet so this change is safe to make. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> --- .../bindings/media/qcom,x1e80100-camss.yaml | 52 +++++++++++++++++----- 1 file changed, 40 insertions(+), 12 deletions(-)