@@ -1090,6 +1090,32 @@ cmu_cpucl0: clock-controller@1ec00000 {
"cluster",
"dbg";
};
+
+ cmu_cpucl1: clock-controller@1ed00000 {
+ compatible = "samsung,exynosautov920-cmu-cpucl1";
+ reg = <0x1ed00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_CPUCL1_SWITCH>,
+ <&cmu_top DOUT_CLKCMU_CPUCL1_CLUSTER>;
+ clock-names = "oscclk",
+ "switch",
+ "cluster";
+ };
+
+ cmu_cpucl2: clock-controller@1ee00000 {
+ compatible = "samsung,exynosautov920-cmu-cpucl2";
+ reg = <0x1ee00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&xtcxo>,
+ <&cmu_top DOUT_CLKCMU_CPUCL2_SWITCH>,
+ <&cmu_top DOUT_CLKCMU_CPUCL2_CLUSTER>;
+ clock-names = "oscclk",
+ "switch",
+ "cluster";
+ };
};
timer {
Add cmu_cpucl1/2(CPU Cluster 1 and CPU Cluster 2) clocks for switch, cluster domains respectively. Signed-off-by: Shin Son <shin.son@samsung.com> --- .../arm64/boot/dts/exynos/exynosautov920.dtsi | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+)