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[RESEND,1/3] spi: tegra210-quad: Add iommus property to DT bindings

Message ID 20250506152350.3370291-1-va@nvidia.com
State New
Headers show
Series [RESEND,1/3] spi: tegra210-quad: Add iommus property to DT bindings | expand

Commit Message

Vishwaroop A May 6, 2025, 3:23 p.m. UTC 
The Tegra210 Quad SPI controller uses internal DMA engines to
efficiently transfer data between system memory and the SPI bus.
On platforms with an IOMMU, such as Tegra234, DMA transactions
must be properly mapped and protected to ensure system security
and functional correctness.

This patch adds the iommus property to the device tree binding.
This property is required to associate the SPI controller with
the system IOMMU, specifying the correct stream ID for address
translation and access protection.

Signed-off-by: Vishwaroop A <va@nvidia.com>
---
 .../devicetree/bindings/spi/nvidia,tegra210-quad.yaml          | 3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
index 48e97e240265..522efbe62010 100644
--- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
@@ -47,6 +47,9 @@  properties:
       - const: rx
       - const: tx
 
+  iommus:
+    maxItems: 1
+
 patternProperties:
   "@[0-9a-f]+$":
     type: object