| Message ID | 20250506180232.1299-5-quic_ptalari@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable QUPs and Serial on SA8255p Qualcomm platforms | expand |
On 06/05/2025 19:02, Praveen Talari wrote: > Enhances code readability and future modifications within the new API. > > Move the code that handles the actual initialization of resources > like clock and ICC paths to a separate function, making the > probe function cleaner. > > Signed-off-by: Praveen Talari <quic_ptalari@quicinc.com> > --- > v3 -> v4 > - added version log after --- > > v1 -> v2 > - updated subject description. > - added a new line after function end > --- > drivers/tty/serial/qcom_geni_serial.c | 66 ++++++++++++++++----------- > 1 file changed, 40 insertions(+), 26 deletions(-) > > diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c > index 0293b6210aa6..6ad759146f71 100644 > --- a/drivers/tty/serial/qcom_geni_serial.c > +++ b/drivers/tty/serial/qcom_geni_serial.c > @@ -1588,6 +1588,43 @@ static struct uart_driver qcom_geni_uart_driver = { > .nr = GENI_UART_PORTS, > }; > > +static int geni_serial_resource_init(struct qcom_geni_serial_port *port) > +{ > + int ret; > + > + port->se.clk = devm_clk_get(port->se.dev, "se"); > + if (IS_ERR(port->se.clk)) { > + ret = PTR_ERR(port->se.clk); > + dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret); > + return ret; > + } > + > + ret = geni_icc_get(&port->se, NULL); > + if (ret) > + return ret; > + > + port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; > + port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; > + > + /* Set BW for register access */ > + ret = geni_icc_set_bw(&port->se); > + if (ret) > + return ret; > + > + ret = devm_pm_opp_set_clkname(port->se.dev, "se"); > + if (ret) > + return ret; > + > + /* OPP table is optional */ > + ret = devm_pm_opp_of_add_table(port->se.dev); > + if (ret && ret != -ENODEV) { > + dev_err(port->se.dev, "invalid OPP table in device tree\n"); > + return ret; > + } > + > + return 0; > +} > + > static void qcom_geni_serial_pm(struct uart_port *uport, > unsigned int new_state, unsigned int old_state) > { > @@ -1690,12 +1727,10 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) > port->dev_data = data; > port->se.dev = &pdev->dev; > port->se.wrapper = dev_get_drvdata(pdev->dev.parent); > - port->se.clk = devm_clk_get(&pdev->dev, "se"); > - if (IS_ERR(port->se.clk)) { > - ret = PTR_ERR(port->se.clk); > - dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); > + > + ret = geni_serial_resource_init(port); > + if (ret) > return ret; > - } > > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > if (!res) > @@ -1713,17 +1748,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) > return -ENOMEM; > } > > - ret = geni_icc_get(&port->se, NULL); > - if (ret) > - return ret; > - port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; > - port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; > - > - /* Set BW for register access */ > - ret = geni_icc_set_bw(&port->se); > - if (ret) > - return ret; > - > port->name = devm_kasprintf(uport->dev, GFP_KERNEL, > "qcom_geni_serial_%s%d", > uart_console(uport) ? "console" : "uart", uport->line); > @@ -1745,16 +1769,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) > if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) > port->cts_rts_swap = true; > > - ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); > - if (ret) > - return ret; > - /* OPP table is optional */ > - ret = devm_pm_opp_of_add_table(&pdev->dev); > - if (ret && ret != -ENODEV) { > - dev_err(&pdev->dev, "invalid OPP table in device tree\n"); > - return ret; > - } > - > port->private_data.drv = drv; > uport->private_data = &port->private_data; > platform_set_drvdata(pdev, port); > -- > 2.17.1 > > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 0293b6210aa6..6ad759146f71 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1588,6 +1588,43 @@ static struct uart_driver qcom_geni_uart_driver = { .nr = GENI_UART_PORTS, }; +static int geni_serial_resource_init(struct qcom_geni_serial_port *port) +{ + int ret; + + port->se.clk = devm_clk_get(port->se.dev, "se"); + if (IS_ERR(port->se.clk)) { + ret = PTR_ERR(port->se.clk); + dev_err(port->se.dev, "Err getting SE Core clk %d\n", ret); + return ret; + } + + ret = geni_icc_get(&port->se, NULL); + if (ret) + return ret; + + port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; + port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; + + /* Set BW for register access */ + ret = geni_icc_set_bw(&port->se); + if (ret) + return ret; + + ret = devm_pm_opp_set_clkname(port->se.dev, "se"); + if (ret) + return ret; + + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(port->se.dev); + if (ret && ret != -ENODEV) { + dev_err(port->se.dev, "invalid OPP table in device tree\n"); + return ret; + } + + return 0; +} + static void qcom_geni_serial_pm(struct uart_port *uport, unsigned int new_state, unsigned int old_state) { @@ -1690,12 +1727,10 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) port->dev_data = data; port->se.dev = &pdev->dev; port->se.wrapper = dev_get_drvdata(pdev->dev.parent); - port->se.clk = devm_clk_get(&pdev->dev, "se"); - if (IS_ERR(port->se.clk)) { - ret = PTR_ERR(port->se.clk); - dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); + + ret = geni_serial_resource_init(port); + if (ret) return ret; - } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) @@ -1713,17 +1748,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) return -ENOMEM; } - ret = geni_icc_get(&port->se, NULL); - if (ret) - return ret; - port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; - port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; - - /* Set BW for register access */ - ret = geni_icc_set_bw(&port->se); - if (ret) - return ret; - port->name = devm_kasprintf(uport->dev, GFP_KERNEL, "qcom_geni_serial_%s%d", uart_console(uport) ? "console" : "uart", uport->line); @@ -1745,16 +1769,6 @@ static int qcom_geni_serial_probe(struct platform_device *pdev) if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) port->cts_rts_swap = true; - ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); - if (ret) - return ret; - /* OPP table is optional */ - ret = devm_pm_opp_of_add_table(&pdev->dev); - if (ret && ret != -ENODEV) { - dev_err(&pdev->dev, "invalid OPP table in device tree\n"); - return ret; - } - port->private_data.drv = drv; uport->private_data = &port->private_data; platform_set_drvdata(pdev, port);
Enhances code readability and future modifications within the new API. Move the code that handles the actual initialization of resources like clock and ICC paths to a separate function, making the probe function cleaner. Signed-off-by: Praveen Talari <quic_ptalari@quicinc.com> --- v3 -> v4 - added version log after --- v1 -> v2 - updated subject description. - added a new line after function end --- drivers/tty/serial/qcom_geni_serial.c | 66 ++++++++++++++++----------- 1 file changed, 40 insertions(+), 26 deletions(-)