| Message ID | 1747401516-286356-1-git-send-email-radhey.shyam.pandey@amd.com |
|---|---|
| State | New |
| Headers | show |
| Series | dt-bindings: usb: dwc3-xilinx: allow dma-coherent | expand |
On Fri, May 16, 2025 at 03:16:02PM +0100, Conor Dooley wrote: > On Fri, May 16, 2025 at 06:48:36PM +0530, Radhey Shyam Pandey wrote: > > On Versal Gen 2 SoC the LPD USB DMA controller is coherent with the CPU > > so allow specifying the information. > > Sounds like it should actually be marked required on this platform, no? Should still work without it, just more overhead of unnecessary cache flushes. Rob
On Fri, 16 May 2025 18:48:36 +0530, Radhey Shyam Pandey wrote: > On Versal Gen 2 SoC the LPD USB DMA controller is coherent with the CPU > so allow specifying the information. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > --- > Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Applied, thanks!
diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml index 379dacacb526..36f5c644d959 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml @@ -26,6 +26,8 @@ properties: ranges: true + dma-coherent: true + power-domains: description: specifies a phandle to PM domain provider node maxItems: 1
On Versal Gen 2 SoC the LPD USB DMA controller is coherent with the CPU so allow specifying the information. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> --- Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 2 ++ 1 file changed, 2 insertions(+) base-commit: 8566fc3b96539e3235909d6bdda198e1282beaed