diff mbox series

[PULL,22/24] hw/misc/stm32_rcc: Fix stm32_rcc_write() arguments order

Message ID 20250610125633.24411-23-philmd@linaro.org
State Accepted
Commit 3938180c9c58b61b38c7fc304eb48b903c7dfd87
Headers show
Series [PULL,01/24] hw/char/sh_serial: Delete fifo_timeout_timer in DeviceUnrealize | expand

Commit Message

Philippe Mathieu-Daudé June 10, 2025, 12:56 p.m. UTC 
From: Philippe Michaud-Boudreault <philmb3487@proton.me>

The tracing function for the write case incorrectly has
parameters switched around. So order them in the correct way.

Signed-off-by: Philippe Michaud-Boudreault <philmb3487@proton.me>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <HnyjTNqwrfGusE44bnM7kuLuj13Di1VgXN-dXVHMOSnfgCUhoipOVIoVS1WQaKrJxmEDy9XJGdlQj6zVTIdJE0QVlfBhfbcckFFWRRP56uY=@proton.me>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/misc/stm32_rcc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/hw/misc/stm32_rcc.c b/hw/misc/stm32_rcc.c
index 94e8dae441c..5815b3efa54 100644
--- a/hw/misc/stm32_rcc.c
+++ b/hw/misc/stm32_rcc.c
@@ -60,7 +60,7 @@  static void stm32_rcc_write(void *opaque, hwaddr addr,
     uint32_t value = val64;
     uint32_t prev_value, new_value, irq_offset;
 
-    trace_stm32_rcc_write(value, addr);
+    trace_stm32_rcc_write(addr, value);
 
     if (addr > STM32_RCC_DCKCFGR2) {
         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",