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From: Sarthak Garg <quic_sartgarg@quicinc.com>
To: Ulf Hansson <ulf.hansson@linaro.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
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Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
quic_cang@quicinc.com, quic_nguyenb@quicinc.com,
quic_rampraka@quicinc.com, quic_pragalla@quicinc.com,
quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com,
quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com,
Sarthak Garg <quic_sartgarg@quicinc.com>
Subject: [PATCH V3 4/4] arm64: dts: qcom: sm8550: Remove SDR104/SDR50 broken
capabilities
Date: Wed, 18 Jun 2025 12:58:18 +0530
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|
| Series |
Add level shifter support for qualcomm SOC's
|
expand
|
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 82cabf777cd2..2c770c979d39 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3180,6 +3180,7 @@ sdhc_2: mmc@8804000 { iommus = <&apps_smmu 0x540 0>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; + max-sd-hs-frequency = <37500000>; power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; @@ -3191,9 +3192,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, bus-width = <4>; dma-coherent; - /* Forbid SDR104/SDR50 - broken hw! */ - sdhci-caps-mask = <0x3 0>; - status = "disabled"; sdhc2_opp_table: opp-table {
Kernel now handles all level shifter limitations related to SD card modes. As a result, the broken hardware capabilities for SDR104 and SDR50 modes can be removed from the device tree. Additionally, due to level shifter constraints, set the maximum frequency for High Speed (HS) mode to 37.5 MHz using the max-sd-hs-frequency property for sm8550. Signed-off-by: Sarthak Garg <quic_sartgarg@quicinc.com> --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)