diff mbox series

[v2,079/101] target/arm: Enable PSEL for SVE2p1

Message ID	20250621235037.74091-80-richard.henderson@linaro.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Subject: [PATCH v2 079/101] target/arm: Enable PSEL for SVE2p1 Date: Sat, 21 Jun 2025 16:50:15 -0700 Message-ID: <20250621235037.74091-80-richard.henderson@linaro.org> In-Reply-To: <20250621235037.74091-1-richard.henderson@linaro.org> References: <20250621235037.74091-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/arm: Implement FEAT_SME2p1 \| expand [v2,000/101] target/arm: Implement FEAT_SME2p1 [v2,001/101] tcg: Add dbase argument to do_dup_store [v2,002/101] tcg: Add dbase argument to do_dup [v2,003/101] tcg: Add dbase argument to expand_clr [v2,004/101] tcg: Add base arguments to check_overlap_[234] [v2,005/101] tcg: Split out tcg_gen_gvec_2_var [v2,006/101] tcg: Split out tcg_gen_gvec_3_var [v2,007/101] tcg: Split out tcg_gen_gvec_mov_var [v2,008/101] tcg: Split out tcg_gen_gvec_{add,sub}_var [v2,009/101] tcg: Split out tcg_gen_gvec_dup_imm_var [v2,010/101] linux-user/aarch64: Update hwcap bits from 6.14 [v2,011/101] target/arm: Remove CPUARMState.vfp.scratch [v2,012/101] target/arm: Introduce FPST_ZA, FPST_ZA_F16 [v2,013/101] target/arm: Use FPST_ZA for sme_fmopa_[hsd] [v2,014/101] target/arm: Rename zarray to za_state.za [v2,015/101] target/arm: Add isar feature tests for SME2, SVE2p1 [v2,016/101] target/arm: Add ZT0 [v2,017/101] target/arm: Add zt0_excp_el to DisasContext [v2,018/101] target/arm: Implement SME2 ZERO ZT0 [v2,019/101] target/arm: Implement SME2 LDR/STR ZT0 [v2,020/101] target/arm: Implement SME2 MOVT [v2,021/101] target/arm: Split get_tile_rowcol argument tile_index [v2,022/101] target/arm: Rename MOVA for translate [v2,023/101] target/arm: Implement SME2 MOVA to/from tile, multiple registers [v2,024/101] target/arm: Split out get_zarray [v2,025/101] target/arm: Implement SME2 MOVA to/from array, multiple registers [v2,026/101] target/arm: Implement SME2 BMOPA [v2,027/101] target/arm: Implement SME2 SMOPS, UMOPS (2-way) [v2,028/101] target/arm: Introduce gen_gvec_sve2_sqdmulh [v2,029/101] target/arm: Implement SME2 Multiple and Single SVE Destructive [v2,030/101] target/arm: Implement SME2 Multiple Vectors SVE Destructive [v2,031/101] target/arm: Implement SME2 ADD/SUB (array results, multiple and single vector) [v2,032/101] target/arm: Implement SME2 ADD/SUB (array results, multiple vectors) [v2,033/101] target/arm: Pass ZA to helper_sve2_fmlal_zz[zx]w_s [v2,034/101] target/arm: Implement SME2 FMLAL, BFMLAL [v2,035/101] target/arm: Implement SME2 FDOT [v2,036/101] target/arm: Implement SME2 BFDOT [v2,037/101] target/arm: Implement SME2 FVDOT, BFVDOT [v2,038/101] target/arm: Rename helper_gvec_dot_[bh] to _4[bh] [v2,039/101] target/arm: Remove helper_gvec_sudot_idx_4b [v2,040/101] target/arm: Implemement SME2 SDOT, UDOT, USDOT, SUDOT [v2,041/101] target/arm: Rename SVE SDOT and UDOT patterns [v2,042/101] target/arm: Tighten USDOT (vectors) decode [v2,043/101] target/arm: Implement SDOT, UDOT (2-way) for SME2/SVE2p1 [v2,044/101] target/arm: Implement SME2 SVDOT, UVDOT, SUVDOT, USVDOT [v2,045/101] target/arm: Implement SME2 SMLAL, SMLSL, UMLAL, UMLSL [v2,046/101] target/arm: Implement SME2 SMLALL, SMLSLL, UMLALL, UMLSLL [v2,047/101] target/arm: Rename gvec_fml[as]_[hs] with _nf_ infix [v2,048/101] target/arm: Implement SME2 FMLA, FMLS [v2,049/101] target/arm: Implement SME2 BFMLA, BFMLS [v2,050/101] target/arm: Implement SME2 FADD, FSUB, BFADD, BFSUB [v2,051/101] target/arm: Implement SME2 BFCVT, BFCVTN, FCVT, FCVTN [v2,052/101] target/arm: Implement SME2 FCVT (widening), FCVTL [v2,053/101] target/arm: Implement SME2 FCVTZS, FCVTZU [v2,054/101] target/arm: Implement SME2 SCVTF, UCVTF [v2,055/101] target/arm: Implement SME2 FRINTN, FRINTP, FRINTM, FRINTA [v2,056/101] target/arm: Introduce do_[us]sat_[bhs] macros [v2,057/101] target/arm: Use do_[us]sat_[bhs] in sve_helper.c [v2,058/101] target/arm: Implement SME2 SQCVT, UQCVT, SQCVTU [v2,059/101] target/arm: Implement SQCVTN, UQCVTN, SQCVTUN for SME2/SVE2p1 [v2,060/101] target/arm: Implement SME2 SUNPK, UUNPK [v2,061/101] target/arm: Implement SME2 ZIP, UZP (four registers) [v2,062/101] target/arm: Move do_urshr, do_srshr to vec_internal.h [v2,063/101] target/arm: Implement SME2 SQRSHR, UQRSHR, SQRSHRN [v2,064/101] target/arm: Implement SME2 ZIP, UZP (two registers) [v2,065/101] target/arm: Implement SME2 FCLAMP, SCLAMP, UCLAMP [v2,066/101] target/arm: Enable SCLAMP, UCLAMP for SVE2p1 [v2,067/101] target/arm: Implement FCLAMP for SME2, SVE2p1 [v2,068/101] target/arm: Implement SME2 SEL [v2,069/101] target/arm: Implement SME2p1 Multiple Zero [v2,070/101] target/arm: Introduce pred_count_test [v2,071/101] target/arm: Fold predtest_ones into helper_sve_brkns [v2,072/101] target/arm: Split out do_whilel from helper_sve_whilel [v2,073/101] target/arm: Split out do_whileg from helper_sve_whileg [v2,074/101] target/arm: Move scale by esz into helper_sve_while* [v2,075/101] target/arm: Split trans_WHILE to lt and gt [v2,076/101] target/arm: Implement SVE2p1 WHILE (predicate pair) [v2,077/101] target/arm: Implement SVE2p1 WHILE (predicate as counter) [v2,078/101] target/arm: Implement SVE2p1 PTRUE (predicate as counter) [v2,079/101] target/arm: Enable PSEL for SVE2p1 [v2,080/101] target/arm: Implement {ADD, SMIN, SMAX, UMIN, UMAX}QV for SVE2p1 [v2,081/101] target/arm: Implement SVE2p1 PEXT [v2,082/101] target/arm: Implement ANDQV, ORQV, EORQV for SVE2p1 [v2,083/101] target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1 [v2,084/101] target/arm: Implement BFMLSLB{L, T} for SME2/SVE2p1 [v2,085/101] target/arm: Implement CNTP (predicate as counter) for SME2/SVE2p1 [v2,086/101] target/arm: Implement DUPQ for SME2p1/SVE2p1 [v2,087/101] target/arm: Implement EXTQ for SME2p1/SVE2p1 [v2,088/101] target/arm: Implement PMOV for SME2p1/SVE2p1 [v2,089/101] target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1 [v2,090/101] target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1 [v2,091/101] target/arm: Implement SME2 counted predicate register load/store [v2,092/101] target/arm: Split the ST_zpri and ST_zprr patterns [v2,093/101] target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1 [v2,094/101] target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h [v2,095/101] target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1 [v2,096/101] target/arm: Implement LD1Q, ST1Q for SVE2p1 [v2,097/101] target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1 [v2,098/101] target/arm: Implement MOVAZ for SME2p1 [v2,099/101] linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1 [v2,100/101] target/arm: Enable FEAT_SME2p1 on -cpu max [v2,101/101] tests/tcg/aarch64: Add sme2-matmul test case

Commit Message

Richard Henderson June 21, 2025, 11:50 p.m. UTC

This instruction is present in both SME(1) and SVE2.1 extensions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/translate-sve.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 43993fd193..e6e2f342ab 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -7261,7 +7261,7 @@  static bool trans_PSEL(DisasContext *s, arg_psel *a)
     TCGv_i64 tmp, didx, dbit;
     TCGv_ptr ptr;
 
-    if (!dc_isar_feature(aa64_sme, s)) {
+    if (!dc_isar_feature(aa64_sme_or_sve2p1, s)) {
         return false;
     }
     if (!sve_access_check(s)) {