| Message ID | 1485434274-6579-3-git-send-email-m.szyprowski@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | Exynos5433/TM2: add clocks configuration for display subsystem | expand |
Hi Marek, 2017-01-26 21:37 GMT+09:00 Marek Szyprowski <m.szyprowski@samsung.com>: > Default clock configuration applied by the bootloader for TM2 and TM2e > boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such > configuration for those boards with 'assigned-clocks*' properties, > parameters for those two additional rates are needed. > > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > --- > drivers/clk/samsung/clk-exynos5433.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c > index 6ee91ae875c3..11343a597093 100644 > --- a/drivers/clk/samsung/clk-exynos5433.c > +++ b/drivers/clk/samsung/clk-exynos5433.c > @@ -739,7 +739,9 @@ > PLL_35XX_RATE(350000000U, 350, 6, 2), > PLL_35XX_RATE(333000000U, 222, 4, 2), > PLL_35XX_RATE(300000000U, 500, 5, 3), > + PLL_35XX_RATE(278000000U, 556, 6, 3), > PLL_35XX_RATE(266000000U, 532, 6, 3), > + PLL_35XX_RATE(250000000U, 500, 6, 3), > PLL_35XX_RATE(200000000U, 400, 6, 3), > PLL_35XX_RATE(166000000U, 332, 6, 3), > PLL_35XX_RATE(160000000U, 320, 6, 3), Acked-by: Chanwoo Choi <cw00.choi@samsung.com> -- Best Regards, Chanwoo Choi Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 6ee91ae875c3..11343a597093 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -739,7 +739,9 @@ PLL_35XX_RATE(350000000U, 350, 6, 2), PLL_35XX_RATE(333000000U, 222, 4, 2), PLL_35XX_RATE(300000000U, 500, 5, 3), + PLL_35XX_RATE(278000000U, 556, 6, 3), PLL_35XX_RATE(266000000U, 532, 6, 3), + PLL_35XX_RATE(250000000U, 500, 6, 3), PLL_35XX_RATE(200000000U, 400, 6, 3), PLL_35XX_RATE(166000000U, 332, 6, 3), PLL_35XX_RATE(160000000U, 320, 6, 3),
Default clock configuration applied by the bootloader for TM2 and TM2e boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such configuration for those boards with 'assigned-clocks*' properties, parameters for those two additional rates are needed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> --- drivers/clk/samsung/clk-exynos5433.c | 2 ++ 1 file changed, 2 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html