@@ -40,6 +40,9 @@ its hardware characteristcs.
- System Trace Macrocell:
"arm,coresight-stm", "arm,primecell"; [1]
+ - Debug Unit:
+ "arm,coresight-debug", "arm,primecell";
+
* reg: physical base address and length of the register
set(s) of the component.
@@ -78,8 +81,10 @@ its hardware characteristcs.
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
- * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
- source is considered to belong to CPU0.
+* Optional properties for ETM/PTM/Debugs:
+
+ * cpu: the cpu phandle this ETM/PTM/Debug is affined to. When omitted
+ the source is considered to belong to CPU0.
* Optional property for TMC:
Adding compatible string for new coresight debug driver. Signed-off-by: Leo Yan <leo.yan@linaro.org> --- Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.7.4