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[Linaro-uefi,v4,1/5] Platforms/Hisilicon/HiKey: append more register definitions

Message ID 1487170499-22374-2-git-send-email-haojian.zhuang@linaro.org
State New
Headers show
Series add drivers for Android Fastboot App on HiKey | expand

Commit Message

Haojian Zhuang Feb. 15, 2017, 2:54 p.m. UTC 
Add more register definitions in Hi6220 SoC.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
---
 Chips/Hisilicon/Hi6220/Include/Hi6220.h | 54 +++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)
diff mbox series

Patch

diff --git a/Chips/Hisilicon/Hi6220/Include/Hi6220.h b/Chips/Hisilicon/Hi6220/Include/Hi6220.h
index 203424a..248de00 100644
--- a/Chips/Hisilicon/Hi6220/Include/Hi6220.h
+++ b/Chips/Hisilicon/Hi6220/Include/Hi6220.h
@@ -23,6 +23,23 @@ 
 #define HI6220_PERIPH_BASE                      0xF4000000
 #define HI6220_PERIPH_SZ                        0x05800000
 
+#define GPIO4_CTRL_BASE                         0xF7020000
+#define GPIO5_CTRL_BASE                         0xF7021000
+#define GPIO6_CTRL_BASE                         0xF7022000
+#define GPIO7_CTRL_BASE                         0xF7023000
+#define GPIO8_CTRL_BASE                         0xF7024000
+#define GPIO9_CTRL_BASE                         0xF7025000
+#define GPIO10_CTRL_BASE                        0xF7026000
+#define GPIO11_CTRL_BASE                        0xF7027000
+#define GPIO12_CTRL_BASE                        0xF7028000
+#define GPIO13_CTRL_BASE                        0xF7029000
+#define GPIO14_CTRL_BASE                        0xF702A000
+#define GPIO15_CTRL_BASE                        0xF702B000
+#define GPIO16_CTRL_BASE                        0xF702C000
+#define GPIO17_CTRL_BASE                        0xF702D000
+#define GPIO18_CTRL_BASE                        0xF702E000
+#define GPIO19_CTRL_BASE                        0xF702F000
+
 #define PERI_CTRL_BASE                          0xF7030000
 #define SC_PERIPH_CTRL4                         0x00C
 #define CTRL4_FPGA_EXT_PHY_SEL                  BIT3
@@ -45,18 +62,47 @@ 
 
 #define SC_PERIPH_CTRL8                         0x018
 #define SC_PERIPH_CLKEN0                        0x200
+
+#define PERIPH_CLKEN0_USBOTG                    BIT4
+
 #define SC_PERIPH_CLKDIS0                       0x204
 #define SC_PERIPH_CLKSTAT0                      0x208
 
+#define SC_PERIPH_CLKEN3                        0x230
 #define SC_PERIPH_RSTEN0                        0x300
 #define SC_PERIPH_RSTDIS0                       0x304
 #define SC_PERIPH_RSTSTAT0                      0x308
+#define SC_PERIPH_RSTEN3                        0x330
+#define SC_PERIPH_RSTDIS3                       0x334
+#define SC_PERIPH_RSTSTAT3                      0x338
 
 #define RST0_USBOTG_BUS                         BIT4
 #define RST0_POR_PICOPHY                        BIT5
 #define RST0_USBOTG                             BIT6
 #define RST0_USBOTG_32K                         BIT7
 
+/* SC_PERIPH_RSTEN0/RSTDIS0/RSTSTAT0 */
+#define PERIPH_RST0_MMC2                        (1 << 2)
+
+/* SC_PERIPH_RSTEN3/RSTDIS3/RSTSTAT3 */
+#define PERIPH_RST3_CSSYS                       (1 << 0)
+#define PERIPH_RST3_I2C0                        (1 << 1)
+#define PERIPH_RST3_I2C1                        (1 << 2)
+#define PERIPH_RST3_I2C2                        (1 << 3)
+#define PERIPH_RST3_I2C3                        (1 << 4)
+#define PERIPH_RST3_UART1                       (1 << 5)
+#define PERIPH_RST3_UART2                       (1 << 6)
+#define PERIPH_RST3_UART3                       (1 << 7)
+#define PERIPH_RST3_UART4                       (1 << 8)
+#define PERIPH_RST3_SSP                         (1 << 9)
+#define PERIPH_RST3_PWM                         (1 << 10)
+#define PERIPH_RST3_BLPWM                       (1 << 11)
+#define PERIPH_RST3_TSENSOR                     (1 << 12)
+#define PERIPH_RST3_DAPB                        (1 << 18)
+#define PERIPH_RST3_HKADC                       (1 << 19)
+#define PERIPH_RST3_CODEC_SSI                   (1 << 20)
+#define PERIPH_RST3_PMUSSI1                     (1 << 22)
+
 #define EYE_PATTERN_PARA                        0x7053348c
 
 #define MDDRC_AXI_BASE                          0xF7120000
@@ -74,4 +120,12 @@ 
 
 #define PMUSSI_BASE                             0xF8000000
 
+#define PMUSSI_REG(x)                           (PMUSSI_BASE + ((x) << 2))
+
+#define GPIO0_CTRL_BASE                         0xF8011000
+#define GPIO1_CTRL_BASE                         0xF8012000
+#define GPIO2_CTRL_BASE                         0xF8013000
+#define GPIO3_CTRL_BASE                         0xF8014000
+
+
 #endif /* __HI6220_H__ */