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[203.254.224.33]) by mx.google.com with ESMTP id vr5si31520633pbc.13.2012.06.19.00.26.00; Tue, 19 Jun 2012 00:26:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5U00B2ZSMRA380@mailout3.samsung.com>; Tue, 19 Jun 2012 16:26:00 +0900 (KST) X-AuditID: cbfee61a-b7f9f6d0000016a8-16-4fe029877cd1 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 1F.C2.05800.78920EF4; Tue, 19 Jun 2012 16:26:00 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5U00EHGSMYFC70@mmp1.samsung.com>; Tue, 19 Jun 2012 16:25:59 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org, dofmind@gmail.com Subject: [PATCH 1/8 V4] EXYNOS: CLK: Add i2c clock Date: Tue, 19 Jun 2012 13:00:25 +0530 Message-id: <1340091032-26560-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340091032-26560-1-git-send-email-rajeshwari.s@samsung.com> References: <1340091032-26560-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jAd0OzQf+Bm82M1k8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DKmP9jD3PBD6GKC6smsjUwHubvYuTkkBAwkdh67x4r hC0mceHeerYuRi4OIYFFjBJX3zxkgXAmMknM+dXIDlLFJmAksfXkNEYQW0RAQuJX/1Uwm1lg CqPErtWhILYwUM2TjWdZQGwWAVWJq9eWgdm8Ah4SHyZPYYLYpiBxbOpXsM2cAp4Sk/bPB4sL AdXc/3KOaQIj7wJGhlWMoqkFyQXFSem5hnrFibnFpXnpesn5uZsYwf5/JrWDcWWDxSFGAQ5G JR7eg3IP/IVYE8uKK3MPMUpwMCuJ8K76f99fiDclsbIqtSg/vqg0J7X4EKM0B4uSOG+T9QV/ IYH0xJLU7NTUgtQimCwTB6dUA+PJOPatGlt3dFTUfPyYarXz/6LnDz/MMQ3d2naKO+dHZc8q 9r3Fh3j/Oe5ViyiymaK0K9RY78dyMc3dehp/K19/+/3yvNusA1lKzKoZnLucju5pMFB0LIq/ Od0mZJ3RVK8jvx73KdZe1etZs+zAu5T+FLM3nsaT2B5xnpJYcW2u2+miLxOOlT9XYinOSDTU Yi4qTgQAhFL6kfsBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQlBAM/Sl7cEusg6rwqBmv0h3MunnoMgqfj8Iuw3ojT5sGFQXKv1qFZ+keF9NVhlPtEK+O9U This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar Signed-off-by: Doug Anderson Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- changes in V2: - Incorporated comments from Simon Glass which are removed extra braces around (readl(&clk->div_top1)) >> 24 and gave a tab space for return statement. Changes in V3: - None Changes in V4: - None arch/arm/cpu/armv7/exynos/clock.c | 33 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..a80928b 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void) writel(cfg, &clk->div_lcd0); } +/* + * I2C + * + * exynos5: obtaining the I2C clock + */ +static unsigned long exynos5_get_i2c_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long aclk_66, aclk_66_pre, sclk; + unsigned int ratio; + + sclk = get_pll_clk(MPLL); + + ratio = (readl(&clk->div_top1)) >> 24; + ratio &= (0x7); + aclk_66_pre = sclk/(ratio+1); + ratio = readl(&clk->div_top0); + ratio &= (0x7); + aclk_66 = aclk_66_pre/(ratio+1); + return aclk_66; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -594,6 +617,16 @@ unsigned long get_arm_clk(void) return exynos4_get_arm_clk(); } +unsigned long get_i2c_clk(void) +{ + if (cpu_is_exynos5()) { + return exynos5_get_i2c_clk(); + } else { + debug("I2C clock is not set for this CPU\n"); + return 0; + } +} + unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..72dc655 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -30,6 +30,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div);