From patchwork Mon Feb 27 18:02:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 94563 Delivered-To: patch@linaro.org Received: by 10.140.20.113 with SMTP id 104csp976922qgi; Mon, 27 Feb 2017 10:04:17 -0800 (PST) X-Received: by 10.237.50.133 with SMTP id z5mr11285032qtd.203.1488218657113; Mon, 27 Feb 2017 10:04:17 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id m9si12376602qte.315.2017.02.27.10.04.16; Mon, 27 Feb 2017 10:04:17 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 27B8960BDF; Mon, 27 Feb 2017 18:04:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 1076D63601; Mon, 27 Feb 2017 18:03:34 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8ED3C635E8; Mon, 27 Feb 2017 18:03:25 +0000 (UTC) Received: from mail-wr0-f179.google.com (mail-wr0-f179.google.com [209.85.128.179]) by lists.linaro.org (Postfix) with ESMTPS id 7A14963603 for ; Mon, 27 Feb 2017 18:02:55 +0000 (UTC) Received: by mail-wr0-f179.google.com with SMTP id u108so27839505wrb.3 for ; Mon, 27 Feb 2017 10:02:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eZl13IcSpt1O7hde4937XViLdu+MLSJBWlLl0OG8lik=; b=kgPHR3b4hdVOtKG0KvdjiR7x48fyZPN5Qv+RDaUUmjQoUAQogls14vuV/xegCydUxR 7H1sZd7nf7Vd4SQg4krHgK/e1/yiR0tKwr98gpFojtBs7pSCoPkp6c/0J7R5zkSKDKjH bpHpljTVNv6mJ2UiDYY/8awGkwIM9hfYLnsZUmMerkrqYeq6hGn/lKnVjR2PRl5sCkyk GDcMhaVF32Y11/trPWmMWlJCcrgnFzil4JtzNwQS4ItO7Dx1KzMunCWZK/QIqRMMX+Fe dIFQNI+997PTd0ets17pp3jGwnXqnC3citQSBGB1iV7Y64gu+W/n8yRcObH+P5cUStji aUPQ== X-Gm-Message-State: AMke39khxfF8ALSuTKpezQs9GF00OBnWNlpwzIek9PhT3PGFvk+dhhf41PKwDMFpFl4Y3IcUHCA= X-Received: by 10.223.134.253 with SMTP id 58mr17913166wry.46.1488218574296; Mon, 27 Feb 2017 10:02:54 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id v72sm12668569wmd.0.2017.02.27.10.02.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 27 Feb 2017 10:02:53 -0800 (PST) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org, leif.lindholm@linaro.org, alan@softiron.co.uk Date: Mon, 27 Feb 2017 18:02:31 +0000 Message-Id: <1488218551-6372-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488218551-6372-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488218551-6372-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH 3/3] Platforms/AMD/Styx: enable strict memory permission policy X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Implement a strict separation between writable and executable memory, by enabling the new core features that - map PE/COFF code and data sections with either executable or writable permissions, but never both; - map all other regions with the XN attributes set. Note that the former requires 4 KB section alignment, which is not the default when using the tiny code model, so set the section alignment explicitly both for DEBUG and RELEASE builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index a236836db691..03ca1ffae2e5 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -273,6 +273,9 @@ DEFINE DO_KCS = 1 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 +[BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION] + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1000 + ################################################################################ # # Pcd Section - list of all EDK II PCD Entries defined by this Platform @@ -440,6 +443,18 @@ DEFINE DO_KCS = 1 ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >= 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM and OS + # reserved ones. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD5 + !if $(DO_PSCI) gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE !else