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[203.254.224.34]) by mx.google.com with ESMTP id hc10si37040638pbc.121.2012.06.20.04.08.54; Wed, 20 Jun 2012 04:08:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout4.samsung.com [203.254.224.34]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5W00A1PXMSJW01@mailout4.samsung.com>; Wed, 20 Jun 2012 20:08:54 +0900 (KST) X-AuditID: cbfee61a-b7f9f6d0000016a8-08-4fe1af453030 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 15.0D.05800.54FA1EF4; Wed, 20 Jun 2012 20:08:53 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5W00K59XJU4P50@mmp1.samsung.com>; Wed, 20 Jun 2012 20:08:53 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, dofmind@gmail.com Subject: [PATCH 7/9 V2] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 Date: Wed, 20 Jun 2012 16:41:53 +0530 Message-id: <1340190715-23648-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340190715-23648-1-git-send-email-rajeshwari.s@samsung.com> References: <1340190715-23648-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOJMWRmVeSWpSXmKPExsVy+t9jAV3X9Q/9DRr/W1s8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DK2PBEqOAQX8W/zjvMDYzvubsYOTgkBEwkFu0U6mLk BDLFJC7cW8/WxcjFISSwiFHiffMHVghnIpPElBMv2EGq2ASMJLaenMYIYosISEj86r/KCFLE LNDBKDHp9BuwhLBAmMT0JzvZQGwWAVWJw3f3sYDYvAIeEsf2vWKCWKcgcWzqV1YQm1PAU2Lp oxVgvUJANZ19M1knMPIuYGRYxSiaWpBcUJyUnmuoV5yYW1yal66XnJ+7iRHs/WdSOxhXNlgc YhTgYFTi4eWZ/dBfiDWxrLgy9xCjBAezkghveQdQiDclsbIqtSg/vqg0J7X4EKM0B4uSOG+T 9QV/IYH0xJLU7NTUgtQimCwTB6dUA+NitQ9u610/PPT/VJTZxDu5+fTEZY/uK709crzpp2RZ 04XnYQ3Fh2cEmvOv3O+lJnn324Yfybrzvz71ZotTdP51VeupRUU718284wWiOte2ZJZPTJ62 Lf2RWPBes1UnDRZM0rdLEbje9q60zGtl9Pp3v6UF+HOa18jeuvkpiUFlet+XHNNL4uuUWIoz Eg21mIuKEwGPHF1Y+gEAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmoTxDH+AeM5RBcC3GMBgj9cEX3641wHaTrsfhRdgyY/0Ab+/jc3XO0Vj8Nexr+UJqnjpVh MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali Signed-off-by: Rajeshwari Shinde --- Chnages in V2: - None arch/arm/cpu/armv7/exynos/clock.c | 12 +++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 3 +++ 2 files changed, 14 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 330bd75..dbd5f11 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq; + unsigned int freq, pll_div2_sel, mpll_fout_sel; switch (pllreg) { case APLL: @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } + /* According to the user manual, in EVT1 MPLL always gives + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ + if (pllreg == MPLL) { + pll_div2_sel = readl(&clk->pll_div2_sel); + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + & MPLL_FOUT_SEL_MASK; + if (mpll_fout_sel == 0) + fout /= 2; + } + return fout; } diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index 7cc3d5e..a34a3f0 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -594,4 +594,7 @@ struct exynos5_clock { unsigned char res109b[0xf5e4]; }; #endif + +#define MPLL_FOUT_SEL_SHIFT 4 +#define MPLL_FOUT_SEL_MASK 0x1 #endif