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[203.254.224.33]) by mx.google.com with ESMTP id he10si579220pbc.198.2012.06.29.04.58.06; Fri, 29 Jun 2012 04:58:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6D00HPTNT816B0@mailout3.samsung.com>; Fri, 29 Jun 2012 20:58:06 +0900 (KST) X-AuditID: cbfee61a-b7f086d000000e64-c1-4fed984df2fd Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 8A.F3.03684.D489DEF4; Fri, 29 Jun 2012 20:58:05 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6D00HDINUORD90@mmp1.samsung.com>; Fri, 29 Jun 2012 20:58:05 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, alim.akhtar@samsung.com, dofmind@gmail.com, jh80.chung@samsung.com Subject: [PATCH 08/10 V3] EXYNOS5: CLOCK: Add BPLL support Date: Fri, 29 Jun 2012 17:30:38 +0530 Message-id: <1340971240-18373-9-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340971240-18373-1-git-send-email-rajeshwari.s@samsung.com> References: <1340971240-18373-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jAV3fGW/9DVpXWVs8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DK+N92nr3glkTFuttXmBsYvwp3MXJwSAiYSPycZNzF yAlkiklcuLeerYuRi0NIYBGjxJHJM5ghnIlMEoc3zmYEqWITMJLYenIamC0iICHxq/8qI0gR M0jH3Z5f7CAJYQEridbeR0wgNouAqsTKP+tZQWxeAQ+Jl/0L2CDWKUgcm/oVLM4p4CkxffYK ZhBbCKjmzONjLBMYeRcwMqxiFE0tSC4oTkrPNdQrTswtLs1L10vOz93ECPb/M6kdjCsbLA4x CnAwKvHwikx66y/EmlhWXJl7iFGCg1lJhHdFC1CINyWxsiq1KD++qDQntfgQozQHi5I4b5P1 BX8hgfTEktTs1NSC1CKYLBMHp1QDo+2BNbf6WlrXvXv/QzCqqkaGv9zbfaZwwaVl9euFGk4v fzZVxmW7457IE3M8ZP5NmHzsyXs7hk8TBBZ973f13OsQVc1tcExx4h/3Or3blhfm88q/3+X7 YsLntkuLLFymMp/uZi1lv2+mvUlVzdpbIHStYZjJ1kTZkiOSahVm+xbOEV6o661Yq8RSnJFo qMVcVJwIAKHXTV/7AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmigsFlKkuw749dlsIDGpzyqasdjd+NIcHwIMnzownvoVM3sxUBxxcEXYPUKtm9NSx91b/c This patch adds support for BPLL clock. Signed-off-b: Rajeshwari Shinde --- Changes in V3: - New Patch. arch/arm/cpu/armv7/exynos/clock.c | 26 ++++++++++++++++++++------ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 2 ++ 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index dbd5f11..13e3641 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq, pll_div2_sel, mpll_fout_sel; + unsigned int freq, pll_div2_sel, fout_sel; switch (pllreg) { case APLL: @@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) r = readl(&clk->vpll_con0); k = readl(&clk->vpll_con1); break; + case BPLL: + r = readl(&clk->bpll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) * MPLL_CON: MIDV [25:16] * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] + * BPLL_CON: MIDV [25:16] */ - if (pllreg == APLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) mask = 0x3ff; else mask = 0x1ff; @@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } - /* According to the user manual, in EVT1 MPLL always gives + /* According to the user manual, in EVT1 MPLL and BPLL always gives * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ - if (pllreg == MPLL) { + if (pllreg == MPLL | pllreg == BPLL) { pll_div2_sel = readl(&clk->pll_div2_sel); - mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + + switch (pllreg) { + case MPLL: + fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) & MPLL_FOUT_SEL_MASK; - if (mpll_fout_sel == 0) + break; + case BPLL: + fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT) + & BPLL_FOUT_SEL_MASK; + break; + } + + if (fout_sel == 0) fout /= 2; } diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..e99339a 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -27,6 +27,7 @@ #define EPLL 2 #define HPLL 3 #define VPLL 4 +#define BPLL 5 unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index bf41c19..fce38ef 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -599,4 +599,6 @@ struct exynos5_clock { #define MPLL_FOUT_SEL_SHIFT 4 #define MPLL_FOUT_SEL_MASK 0x1 +#define BPLL_FOUT_SEL_SHIFT 0 +#define BPLL_FOUT_SEL_MASK 0x1 #endif