From patchwork Fri Jun 29 12:59:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 9710 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2C30423E40 for ; Fri, 29 Jun 2012 12:56:21 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id EFCE0A18749 for ; Fri, 29 Jun 2012 12:56:20 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so2916581ggn.11 for ; Fri, 29 Jun 2012 05:56:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=MSPB6sa5M8xCpgFmXuvqHyd2TrK2UBX19WJQrfWMtqM=; b=kttUX5fVhRwgOgt0h1JNQZWKBsDFeS6PViC2D3GZfpypOGTUptgFwuXjdEq4A6l9wN U9FFvkN4O9xWPn5Ww5r+vI8bbtxJK2NBXvbkWC+jddzIkOTdDZ4L/UEYLDjV0feN+GO8 wPP36ziQu2/VzZr7HuWAF4M9p3QsS+7bt24nX+d2KoM/550QUSq1JXncJHYoiE6OlfOE NQ0cxFJuJ6WPyCx6oy8J1yWKQ0JlzYs0kzInnP6G2HXzutxiR9FDcDmWhtHiyPpxJkIg V/9nijiboU0u+LpW3yd1qMSA2RkP58XppDIYz7OCb+N+i3oXvpOrPAYb4zTODieDDzdQ FfEg== Received: by 10.50.193.196 with SMTP id hq4mr1308954igc.57.1340974579356; Fri, 29 Jun 2012 05:56:19 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp90896ibb; Fri, 29 Jun 2012 05:56:18 -0700 (PDT) Received: by 10.68.240.73 with SMTP id vy9mr6923051pbc.102.1340974578524; Fri, 29 Jun 2012 05:56:18 -0700 (PDT) Received: from mailout2.samsung.com (mailout2.samsung.com. [203.254.224.25]) by mx.google.com with ESMTP id qd2si8178812pbb.297.2012.06.29.05.56.18; Fri, 29 Jun 2012 05:56:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) client-ip=203.254.224.25; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.25 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout2.samsung.com [203.254.224.25]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6D00106QKL8FD0@mailout2.samsung.com>; Fri, 29 Jun 2012 21:56:17 +0900 (KST) X-AuditID: cbfee61b-b7f776d000002f3f-49-4feda5f178e9 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 52.2E.12095.1F5ADEF4; Fri, 29 Jun 2012 21:56:17 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6D00JE7QK7T260@mmp2.samsung.com>; Fri, 29 Jun 2012 21:56:17 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, alim.akhtar@samsung.com, dofmind@gmail.com, jh80.chung@samsung.com Subject: [PATCH 08/10 V4] EXYNOS5: CLOCK: Add BPLL support Date: Fri, 29 Jun 2012 18:29:08 +0530 Message-id: <1340974750-19969-9-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340974750-19969-1-git-send-email-rajeshwari.s@samsung.com> References: <1340974750-19969-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJJMWRmVeSWpSXmKPExsVy+t9jQd2PS9/6G8yZxGfxcP1NFosph7+w ODB53Lm2hy2AMYrLJiU1J7MstUjfLoErY1b3DaaCWZIVT9/OZmlgnCPSxcjJISFgIrHs3hlG CFtM4sK99WxdjFwcQgLTGSWurLzKDOFMZJK4fHQiM0gVm4CRxNaT08A6RAQkJH71X2UEKWIW WMQocbfnFztIQljASmLZ1u1sIDaLgKpEx5XnYHFeAQ+J/fvmQq1TkDg29SsriM0p4CnxZFMT mC0EVPPizUXWCYy8CxgZVjGKphYkFxQnpeca6RUn5haX5qXrJefnbmIEB8Az6R2MqxosDjEK cDAq8fAqLHrrL8SaWFZcmXuIUYKDWUmE9+FioBBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHeJusL /kIC6YklqdmpqQWpRTBZJg5OqQZGNtf+8si/58ozrWM4r17g+/eWo+eM/JqimyaRkZqSCxRO V+/cf0vry72jB1Oc5UL3mLy3lTefl7OzMFiobZYtm2XKlmn1Bo3OoZ+v7v0wb52gxkV2X1Gm yS4zJd7I3FT1D98R8napp1GLrmHGGxGfW7Z7mP/Hdl/fmMjeJ3BM8NE7pzkH189SYinOSDTU Yi4qTgQAFS7BFPwBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmkxPWO+kSbXPjkrVdu/MFTxRYFEFcWxq+AIFuKPBPXbvNlxgTEwP1NsGZcvB3vbcia+4Wt This patch adds support for BPLL clock. Signed-off-by: Rajeshwari Shinde Acked-by: Joonyoung Shim --- Changes in V3: - New Patch Changes in V4: - Removed the warning message. arch/arm/cpu/armv7/exynos/clock.c | 26 ++++++++++++++++++++------ arch/arm/include/asm/arch-exynos/clk.h | 1 + arch/arm/include/asm/arch-exynos/clock.h | 2 ++ 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index dbd5f11..13e3641 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq, pll_div2_sel, mpll_fout_sel; + unsigned int freq, pll_div2_sel, fout_sel; switch (pllreg) { case APLL: @@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) r = readl(&clk->vpll_con0); k = readl(&clk->vpll_con1); break; + case BPLL: + r = readl(&clk->bpll_con0); + break; default: printf("Unsupported PLL (%d)\n", pllreg); return 0; @@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg) * MPLL_CON: MIDV [25:16] * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] + * BPLL_CON: MIDV [25:16] */ - if (pllreg == APLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) mask = 0x3ff; else mask = 0x1ff; @@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg) fout = m * (freq / (p * (1 << (s - 1)))); } - /* According to the user manual, in EVT1 MPLL always gives + /* According to the user manual, in EVT1 MPLL and BPLL always gives * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ - if (pllreg == MPLL) { + if (pllreg == MPLL || pllreg == BPLL) { pll_div2_sel = readl(&clk->pll_div2_sel); - mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) + + switch (pllreg) { + case MPLL: + fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT) & MPLL_FOUT_SEL_MASK; - if (mpll_fout_sel == 0) + break; + case BPLL: + fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT) + & BPLL_FOUT_SEL_MASK; + break; + } + + if (fout_sel == 0) fout /= 2; } diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 637fb4b..e99339a 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -27,6 +27,7 @@ #define EPLL 2 #define HPLL 3 #define VPLL 4 +#define BPLL 5 unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index bf41c19..fce38ef 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -599,4 +599,6 @@ struct exynos5_clock { #define MPLL_FOUT_SEL_SHIFT 4 #define MPLL_FOUT_SEL_MASK 0x1 +#define BPLL_FOUT_SEL_SHIFT 0 +#define BPLL_FOUT_SEL_MASK 0x1 #endif