Toggle navigation
Patchwork
Patches credited to richard.henderson@linaro.org
Login
Register
Mail settings
Current Team Memberships
team-tcwg
Show patches with
: Series =
target/openrisc improvements
| Archived =
No
| 23 patches
Series
Submitter
State
any
Action Required
New
Under Review
Accepted
Rejected
RFC
Not Applicable
Changes Requested
Awaiting Upstream
Superseded
Deferred
Search
Archived
No
Yes
Both
Apply
Patch
Series
S/W/F
Date
Submitter
Delegate
State
[v3,23/23] linux-user: Fix struct sigaltstack for openrisc
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
New
[v3,22/23] linux-user: Implement signals for openrisc
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
New
[v3,21/23] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,20/23] target/openrisc: Reorg tlb lookup
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
New
[v3,19/23] target/openrisc: Increase the TLB size
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
New
[v3,18/23] target/openrisc: Stub out handle_mmu_fault for softmmu
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,17/23] target/openrisc: Use identical sizes for ITLB and DTLB
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,16/23] target/openrisc: Fix cpu_mmu_index
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,15/23] target/openrisc: Fix tlb flushing in mtspr
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,14/23] target/openrisc: Reduce tlb to a single dimension
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,13/23] target/openrisc: Merge mmu_helper.c into mmu.c
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
New
[v3,12/23] target/openrisc: Remove indirect function calls for mmu
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
New
[v3,11/23] target/openrisc: Merge tlb allocation into CPUOpenRISCState
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,10/23] target/openrisc: Form the spr index from tcg
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,09/23] target/openrisc: Exit the TB after l.mtspr
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,08/23] target/openrisc: Split out is_user
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,07/23] target/openrisc: Link more translation blocks
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,06/23] target/openrisc: Fix singlestep_enabled
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,05/23] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,04/23] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,03/23] target/openrisc: Log interrupts
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,02/23] target/openrisc: Add print_insn_or1k
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
[v3,01/23] target/openrisc: Fix mtspr shadow gprs
target/openrisc improvements
-
-
-
2018-06-28
Richard Henderson
Superseded
Bundling
Create bundle: