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Show patches with: Archived = No       |   48 patches
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Patch Series S/W/F Date Submitter Delegate State
ARM64: Splitting GenerateDivRem* functions into GenerateIntDiv and GenerateIntRem functions --- 2018-06-13 Evgeny Astigeevich Accepted
ARM64: Optimization of HRem and HDiv when a denominator is power of 2 --- 2018-06-25 Evgeny Astigeevich Accepted
ART: Refactor Int64ConstantFrom to use Int64FromConstant; rename it to Int64FromLocation --- 2018-06-27 Evgeny Astigeevich Accepted
ART: Delete code optimizing a%1 and a%-1 from InstructionCodeGeneratorARM64 --- 2018-06-27 Evgeny Astigeevich Accepted
Fix: unknown pragma 'clang optimize' error when g++ is used for building VIXL tests --- 2018-06-27 Evgeny Astigeevich Accepted
[ART tools] Fix construction of a make target string to build public.libraries.txt --- 2018-09-05 Evgeny Astigeevich Accepted
[ART] Make killing logd more safe --- 2018-09-24 Evgeny Astigeevich Accepted
ART: Add CRC32.udate(int,int) intrinsic for ARM64 --- 2018-11-01 Evgeny Astigeevich Accepted
Fix error: undefined symbol art::instruction_set_details::GetStackOverflowReservedBytesFailure --- 2018-11-16 Evgeny Astigeevich Accepted
ART: Add CRC32.updateBytes intrinsic for ARM64 --- 2018-12-04 Evgeny Astigeevich Accepted
ART: Enable ISA features run-time detection for ARM64 --- 2018-12-12 Evgeny Astigeevich Accepted
ART: Optimize use of registers for CRC32.update intrinsic --- 2018-12-17 Evgeny Astigeevich Accepted
ART: Correct attributes of CRC32Update intrinsic --- 2018-12-17 Evgeny Astigeevich Accepted
ART: Add CRC32.updateByteBuffer intrinsic for ARM64 --- 2018-12-19 Evgeny Astigeevich Accepted
ART: Replace 'auto' with actual types --- 2019-01-08 Evgeny Astigeevich Accepted
ART: add running gtests in parallel to run-gtests.sh --- 2019-02-11 Evgeny Astigeevich New
Fix MaskAddresses for toybox sed --- 2019-02-28 Evgeny Astigeevich Accepted
ART: Refactor SchedulingGraph for consistency and clarity --- 2019-04-02 Evgeny Astigeevich Accepted
Fix race condition in using classes.dex --- 2019-05-03 Evgeny Astigeevich Rejected
Fix uses of MaybeRecordImplicitNullCheck without special scopes --- 2019-10-07 Evgeny Astigeevich Accepted
Add GetScratchVRegisterList to help ART to move to new API --- 2019-10-15 Evgeny Astigeevich Accepted
Fix intersecting live ranges created by instruction scheduler --- 2019-10-28 Evgeny Astigeevich Accepted
ARM64: Move from FPRegister to VRegister based API --- 2019-10-31 Evgeny Astigeevich Accepted
Merge 'master' of https://git.linaro.org/arm/vixl --- 2019-11-04 Evgeny Astigeevich Accepted
Add ImprovedOptimizingUnitTest::CreateParameters for subclasses --- 2019-12-12 Evgeny Astigeevich Accepted
Add OptimizingUnitTestHelper::GraphChecker methods --- 2020-01-06 Evgeny Astigeevich Accepted
Enable support of VecLoad/VecStore in LSE --- 2020-01-27 Evgeny Astigeevich Accepted
Disable Dex2oatSwapUseTest.CheckSwapUsage for x86_64 --- 2020-01-29 Evgeny Astigeevich Accepted
ART: Add workaround of 4.14 kernel bug to 137-cfi --- 2020-02-25 Evgeny Astigeevich Accepted
ART: Refactor InstructionCodeGeneratorARM64::GenerateDivRemWithAnyConstant --- 2020-05-06 Evgeny Astigeevich Accepted
ARM64: Combine LSR+ASR into ASR for Int32 HDiv/HRem --- 2020-05-11 Evgeny Astigeevich Accepted
ART: Optimize ADD/SUB+ADD_shift into ADDS/SUBS+CINC for HDiv/HRem --- 2020-05-14 Evgeny Astigeevich Accepted
ARM64: Combine LSR+ADD into ADD_shift for Int32 HDiv/HRem --- 2020-05-18 Evgeny Astigeevich Accepted
ART: Fix infinite recursion in testrunner parse_test_name --- 2020-05-18 Evgeny Astigeevich Accepted
ARM64: Msub strength reduction for HRem --- 2020-05-19 Evgeny Astigeevich Rejected
ART: Add classes having intrinsics to boot image --- 2020-05-28 Evgeny Astigeevich Accepted
ART: Add be_loop_friendly flag to OptimizationDef --- 2020-06-03 Evgeny Astigeevich Rejected
ART: Simplify HRem to reuse existing HDiv --- 2020-06-12 Evgeny Astigeevich Accepted
ART: Add recognition of optimized HRems in BCE --- 2020-06-17 Evgeny Astigeevich Accepted
ART: Transform Sub+Sub into Sub+Add to merge Shl --- 2020-06-17 Evgeny Astigeevich Accepted
ARM32: Combine LSR into ADD for Div by 2^n --- 2020-06-25 Evgeny Astigeevich Accepted
ARM: Optimize Div/Rem by 2^n for non-negative dividends --- 2020-06-30 Evgeny Astigeevich Accepted
ARM: Optimize Div/Rem by positive const for non-negative dividends --- 2020-07-02 Evgeny Astigeevich Accepted
Dump ISA into .cfg --- 2020-07-27 Evgeny Astigeevich Accepted
Fix missing return in non-void TransformArrayRef::end --- 2020-07-29 Evgeny Astigeevich Accepted
ART: Add HasNonNegativeInputAt and HasNonNegativeOrMinIntInputAt --- 2020-08-12 Evgeny Astigeevich Accepted
ARM: Optimize div/rem when dividends are non-negative loop counters --- 2020-08-18 Evgeny Astigeevich New
ARM: Optimize div/rem when dividend is compared with a non-negative --- 2020-09-14 Evgeny Astigeevich Accepted

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