From patchwork Tue Oct 18 13:10:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 78024 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp881567qge; Tue, 18 Oct 2016 06:18:49 -0700 (PDT) X-Received: by 10.55.25.211 with SMTP id 80mr448392qkz.230.1476796729904; Tue, 18 Oct 2016 06:18:49 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id 38si20947348qtv.117.2016.10.18.06.18.49; Tue, 18 Oct 2016 06:18:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 902BA60C1A; Tue, 18 Oct 2016 13:18:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 53C0D61588; Tue, 18 Oct 2016 13:13:11 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 35CC560AF3; Tue, 18 Oct 2016 13:12:36 +0000 (UTC) Received: from mail-pf0-f172.google.com (mail-pf0-f172.google.com [209.85.192.172]) by lists.linaro.org (Postfix) with ESMTPS id 7726860AF3 for ; Tue, 18 Oct 2016 13:11:57 +0000 (UTC) Received: by mail-pf0-f172.google.com with SMTP id e6so94377946pfk.3 for ; Tue, 18 Oct 2016 06:11:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yVOXLNQQ9l4f6UkS0hprQ+r6kFSMU2XOxxJ+m7SxlnA=; b=a2FaRqKOxw+f0e2uSB5V9c5bRKZ//nqIuGAWbvrmMBUUYGghB5WaE0jrr9/NegxNLI xVYVfPW+OBbd65agtRA/ibCpowCDCaKaXi4zpszzptt3XMSdNG6NOHhB8CAtoazPKAfA sW/aad3KjANpmIhOw++NpFL9WF7tPh6U4tGY8rWJEATUI1C+yUCMFjqtpDbyLlJd20Q8 Rl2wn/JdPUEgJdTWgjSSsDA0r5D1Zo1B/sL89e/uGZH/4E4zMlG5mjrxgBA0USplVhnb AFMcTnNFaEgqowRpMyBkZGIt8aHYxskCCERDzHAkBiDOu21OCSpC5+NSybvHXmF/MysI jeiQ== X-Gm-Message-State: AA6/9RnsgMnvhlXRoJr0OgonW+izTb0geKdztSJdKzKHxjaA6XnLlcYiLgBFm9rzqE+YK/dfTDY= X-Received: by 10.98.150.137 with SMTP id s9mr568609pfk.135.1476796316840; Tue, 18 Oct 2016 06:11:56 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a88sm56088460pfe.21.2016.10.18.06.11.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Oct 2016 06:11:56 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Tue, 18 Oct 2016 21:10:00 +0800 Message-Id: <1476796207-94336-17-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> References: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH v2 16/24] Hisilicon/PlatformSysCtrlLib: add more interfaces to support D05 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" System initialization on D05 has some differences from that on D02 and D03, so we extract more platform system control interfaces to support D05 within the same architectural modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h index f374112..1ad9c87 100644 --- a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h +++ b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h @@ -90,8 +90,17 @@ VOID DResetUsb (); UINT32 PlatformGetEhciBase (); UINT32 PlatformGetOhciBase (); VOID PlatformPllInit(); +// PLL initialization for super IO clusters. +VOID SiclPllInit(UINT32 SclId); VOID PlatformDeviceDReset(); VOID PlatformGicdInit(); VOID PlatformLpcInit(); +// Synchronize architecture timer counter between different super computing +// clusters. +VOID PlatformArchTimerSynchronize(); +VOID PlatformEventBroadcastConfig(); +UINTN GetDjtagRegBase(UINT32 NodeId); +VOID LlcCleanInvalidateAsm(); +VOID PlatformMdioInit(); #endif