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Tue, 18 Oct 2016 06:11:27 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a88sm56088460pfe.21.2016.10.18.06.11.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Oct 2016 06:11:27 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Tue, 18 Oct 2016 21:09:47 +0800 Message-Id: <1476796207-94336-4-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> References: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> Cc: hensonwang Subject: [Linaro-uefi] [PATCH v2 03/24] Hisilicon/Hi1610/PCIe: Added performance tuning X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Modify PCIe transaction memory attribute to improve performance, like SMMU bypass, cache snoopy, etc. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang Signed-off-by: Heyi Guo --- .../Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 ++ .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 47 ++++++++++++++++++++++ Chips/Hisilicon/HisiPkg.dec | 1 + Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 1 + Platforms/Hisilicon/D03/D03.dsc | 1 + 5 files changed, 53 insertions(+) mode change 100755 => 100644 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index 63d8bb1..8659e29 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -53,6 +53,9 @@ gHisiTokenSpaceGuid.Pcdsoctype gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress +[FeaturePcd] + gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable + [depex] TRUE diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c old mode 100755 new mode 100644 index 5c14907..3a2bee0 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -21,6 +21,8 @@ #include #include +#define PCIE_SYS_REG_OFFSET 0x1000 + static PCIE_INIT_CFG mPcieIntCfg; UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; UINT64 pcie_subctrl_base_1610[2] = {0xa0000000, 0xb0000000}; @@ -185,6 +187,49 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) } +STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) +{ + UINT32 Value; + UINTN RegSegmentOffset; + + if(Port >= PCIE_MAX_PORT_NUM) + { + return EFI_INVALID_PARAMETER; + } + + RegSegmentOffset = PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET; + + //Enable SMMU bypass for translation + RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); + //BIT13: controller master read SMMU bypass + //BIT12: controller master write SMMU bypass + //BIT10: SMMU bypass enable + Value |= (BIT13 | BIT12 | BIT10); + RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); + + //Switch strongly order (SO) to relaxed order (RO) for write transaction + RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value); + //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write acknowledge + //BIT17 | BIT19 | BIT21 | BIT23 | BIT25 | BIT27 | BIT29: Enable RO for all types of write transaction + Value |= (BIT13 | BIT12 | BIT17 | BIT19 | BIT21 | BIT23 | BIT25 | BIT27 | BIT29); + RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value); + + //Force streamID for controller read operation + RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); + //Force using streamID in PCIE_SYS_CTRL54_REG + Value &= ~(BIT30); + //Set streamID to 0, bit[0:15] is for request ID and should be kept + Value &= ~(0xff<<16); + RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); + + //Enable read and write snoopy + RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); + Value |= (BIT28 | BIT30); + RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); + + return EFI_SUCCESS; +} + EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { PCIE_CTRL_7_U pcie_ctrl7; @@ -940,6 +985,8 @@ PciePortInit ( /* assert LTSSM enable */ (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); + if (FeaturePcdGet (PcdIsPciPerfTuningEnable)) + (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex); PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex); /* diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 8e46e0d..2ce60d9 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -161,6 +161,7 @@ gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056 [PcdsFeatureFlag] + gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066 diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index bdd80f8..539d567 100644 --- a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -8981,6 +8981,7 @@ typedef union tagIepMsiCtrlIntStatus #define PCIE_SYS_CTRL24_REG (PCI_SYS_BASE + 0x1b4) #define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4) #define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8) +#define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274) #define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30) #define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34) #define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38) diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 6d82627..942b2b8 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -111,6 +111,7 @@ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"