From patchwork Tue Oct 18 13:09:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 78013 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp878795qge; Tue, 18 Oct 2016 06:13:17 -0700 (PDT) X-Received: by 10.200.45.124 with SMTP id o57mr441291qta.90.1476796397496; Tue, 18 Oct 2016 06:13:17 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id l67si14633951qkf.317.2016.10.18.06.13.16; Tue, 18 Oct 2016 06:13:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id D77D7615C4; Tue, 18 Oct 2016 13:13:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 698E360DCD; Tue, 18 Oct 2016 13:12:12 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id DB83360DCE; Tue, 18 Oct 2016 13:12:03 +0000 (UTC) Received: from mail-pf0-f172.google.com (mail-pf0-f172.google.com [209.85.192.172]) by lists.linaro.org (Postfix) with ESMTPS id 10DAA60B25 for ; Tue, 18 Oct 2016 13:11:30 +0000 (UTC) Received: by mail-pf0-f172.google.com with SMTP id s8so94685532pfj.2 for ; Tue, 18 Oct 2016 06:11:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KklWjYER9dLpZ5ChIAzlUdvfRrEqrVd/kSX+m9uV2rI=; b=a6o6y8VhXypc5YWtnZvXsY1t+Jwtq6I71j7fg6SQlv/khRdRSsDdNZapRxTKBn031B OJrNZVfpK9G43INH9VxSkQtT85ab6iogb0Uy1bEmn+0EukRoJsnPO1z71TybyDuDUEr0 3FPJr+SuqWAMnYXQIOXwfqJlv2ti2lofr+JJ4Wxi2ErvEXC7OfolkaaSZSSb2Jyndky2 QIniizGKTd0926hXvNxUK47Ne2/Ltnw9y1ZmI5GnJ1ZsCkyTbr2mnhWPwZHN1m1OTNGm LAFxnoNTPNlW04JQgpA4KGZ6J5tSyueGKvtlcOzPScx/7tq0hSySWv33nK5JQlt/l/El lPrA== X-Gm-Message-State: AA6/9Rld4yZT6LztoijOjp5N5JcWdZgzeUHq3sNfe8FlmJQhxQwEcV1sRFsQDQ6AVoygCHieCMk= X-Received: by 10.98.36.219 with SMTP id k88mr645157pfk.88.1476796289380; Tue, 18 Oct 2016 06:11:29 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a88sm56088460pfe.21.2016.10.18.06.11.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Oct 2016 06:11:28 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Tue, 18 Oct 2016 21:09:48 +0800 Message-Id: <1476796207-94336-5-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> References: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> Cc: hensonwang Subject: [Linaro-uefi] [PATCH v2 04/24] Hisilicon/Hi1610/PCIe: Remove lane reversal code X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Lane reversal is the default setting of chip and it is unnecessary for software to do that. We made a mistake to do it in software, and this patch is to remove the duplication. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 1 - 1 file changed, 1 deletion(-) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 3a2bee0..730bdb0 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -971,7 +971,6 @@ PciePortInit ( (VOID)PciePcsInit(soctype, HostBridgeNum, PortIndex); (VOID)PcieModeSet(soctype, HostBridgeNum, PortIndex,PcieCfg->PortInfo.PortType); - (VOID)PcieLaneReversalSet(soctype, HostBridgeNum, PortIndex); (VOID)PcieSpdSet(soctype, HostBridgeNum, PortIndex, 3); (VOID)PciePortNumSet(soctype, HostBridgeNum, PortIndex, 0); /* setup root complex */