From patchwork Sat Nov 19 08:37:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 83064 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp499969qge; Sat, 19 Nov 2016 00:40:56 -0800 (PST) X-Received: by 10.107.169.150 with SMTP id f22mr3622343ioj.7.1479544856567; Sat, 19 Nov 2016 00:40:56 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id q79si8160645iod.143.2016.11.19.00.40.55; Sat, 19 Nov 2016 00:40:56 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 904C960E9C; Sat, 19 Nov 2016 08:40:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 062EB60CC3; Sat, 19 Nov 2016 08:39:33 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 1D28D608F0; Sat, 19 Nov 2016 08:39:26 +0000 (UTC) Received: from mail-pg0-f44.google.com (mail-pg0-f44.google.com [74.125.83.44]) by lists.linaro.org (Postfix) with ESMTPS id CAB2A604A1 for ; Sat, 19 Nov 2016 08:39:24 +0000 (UTC) Received: by mail-pg0-f44.google.com with SMTP id f188so111031512pgc.3 for ; Sat, 19 Nov 2016 00:39:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T+oPWPHyTtYoJOThQnvLcSEjPEoeo0oYc0g0MS5jJVQ=; b=BUU9rix3jkix7fKRqbAaiIimJPpoKRxXYfLOsyr17UbFw4OdcQ78oOB6tTkIpfjdL7 ilvmgMnCq2LWMRa24w3LyaNpF13pyQWtuUuvXbx5c5xHnFqpeWL76zr1KOEJvAVZq7rb WhDh3OL0coRTYQ3X97lvlXPgqDu5ASVMMSZVbgs6RPrPJmGSXd4xS0aDgaPY0UzmLtPa D41W1bHH5JNuTaKrHaET8m0ISwZEoDi3fjfLRYDk5yXpqhe2rXPq6j1KpcGwhywCmb+h UkOACy81OE/UJFtkLPqDjsKO/WEepoL3OAySlg0OagSF/dsRXHW+kTkICacrgJQdc40d 7pnA== X-Gm-Message-State: AKaTC020wQOtXYP4PI/SuF6XtwYYxj0ao4fnk0969v2K+LfXZ9Rv7aKIzmtzaVwEF1aT2bkDo0E= X-Received: by 10.98.10.198 with SMTP id 67mr4984972pfk.157.1479544764087; Sat, 19 Nov 2016 00:39:24 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id v193sm5106241pgb.37.2016.11.19.00.39.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 19 Nov 2016 00:39:23 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Sat, 19 Nov 2016 16:37:17 +0800 Message-Id: <1479544691-59575-3-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> References: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> Cc: hensonwang Subject: [Linaro-uefi] [Patch v4 02/56] Hisilicon/Hi1610/PCIe: Add performace tuning X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Modify PCIe transaction memory attribute to improve performance, like SMMU bypass, cache snoopy, etc. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- .../Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 ++ .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 52 ++++++++++++++++++++++ Chips/Hisilicon/HisiPkg.dec | 1 + Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 1 + Platforms/Hisilicon/D03/D03.dsc | 1 + 5 files changed, 58 insertions(+) mode change 100755 => 100644 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index 63d8bb1..8659e29 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -53,6 +53,9 @@ gHisiTokenSpaceGuid.Pcdsoctype gHisiTokenSpaceGuid.PcdPcieMsiTargetAddress +[FeaturePcd] + gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable + [depex] TRUE diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c old mode 100755 new mode 100644 index 06ecf87..39b9ea7 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -21,6 +21,8 @@ #include #include +#define PCIE_SYS_REG_OFFSET 0x1000 + static PCIE_INIT_CFG mPcieIntCfg; UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; UINT64 pcie_subctrl_base_1610[2] = {0xa0000000, 0xb0000000}; @@ -185,6 +187,50 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) } +STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) +{ + UINT32 Value; + UINTN RegSegmentOffset; + + if (Port >= PCIE_MAX_ROOTBRIDGE) { + DEBUG((DEBUG_ERROR, "Invalid port number: %d\n", Port)); + return EFI_INVALID_PARAMETER; + } + + RegSegmentOffset = PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET; + + //Enable SMMU bypass for translation + RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); + //BIT13: controller master read SMMU bypass + //BIT12: controller master write SMMU bypass + //BIT10: SMMU bypass enable + Value |= (BIT13 | BIT12 | BIT10); + RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); + + //Switch strongly order (SO) to relaxed order (RO) for write transaction + RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value); + //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write acknowledge + Value |= (BIT13 | BIT12); + //BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17: Enable RO for all types of write transaction + Value |= (BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17); + RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value); + + //Force streamID for controller read operation + RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); + //Force using streamID in PCIE_SYS_CTRL54_REG + Value &= ~(BIT30); + //Set streamID to 0, bit[0:15] is for request ID and should be kept + Value &= ~(0xff << 16); + RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); + + //Enable read and write snoopy + RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); + Value |= (BIT30 | BIT28); + RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); + + return EFI_SUCCESS; +} + EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) { PCIE_CTRL_7_U pcie_ctrl7; @@ -939,6 +985,12 @@ PciePortInit ( /* assert LTSSM enable */ (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); + if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { + //PCIe will still work even if performance tuning fails, + //and there is warning message inside the function to print + //detailed error if there is. + (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex); + } PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex); /* diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec index 8e46e0d..2ce60d9 100644 --- a/Chips/Hisilicon/HisiPkg.dec +++ b/Chips/Hisilicon/HisiPkg.dec @@ -161,6 +161,7 @@ gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|0|UINT32|0x40000056 [PcdsFeatureFlag] + gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066 diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index bdd80f8..539d567 100644 --- a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -8981,6 +8981,7 @@ typedef union tagIepMsiCtrlIntStatus #define PCIE_SYS_CTRL24_REG (PCI_SYS_BASE + 0x1b4) #define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4) #define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8) +#define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274) #define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30) #define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34) #define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38) diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 6d82627..942b2b8 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -111,6 +111,7 @@ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"