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[54.225.227.206]) by mx.google.com with ESMTP id d54si2006818qta.294.2016.12.01.20.30.07; Thu, 01 Dec 2016 20:30:08 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 057AC60E95; Fri, 2 Dec 2016 04:30:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 03D836081F; Fri, 2 Dec 2016 04:19:17 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id B501E62DA2; Fri, 2 Dec 2016 04:19:12 +0000 (UTC) Received: from mail-pf0-f172.google.com (mail-pf0-f172.google.com [209.85.192.172]) by lists.linaro.org (Postfix) with ESMTPS id 6149262EB7 for ; Fri, 2 Dec 2016 04:15:31 +0000 (UTC) Received: by mail-pf0-f172.google.com with SMTP id i88so49983937pfk.2 for ; Thu, 01 Dec 2016 20:15:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qDfdJfeTO5UH59xX+Xf4+MqohpdnM/JA4uOpbAT1Xp4=; b=bONNKrf96yiKytv8DupAk8kK3rkjj34h96LcXgzCqJy8a74V5omGnFh1ncht7mtU9n U8TpYSutNcub1G9lNDn+WTgMFZ3Wfcd7S2IGQ/Ql6Bl0drKWYsw/LZY2Gq5abiQZIiPj U5qtWAOxQLFl17dWbCWnSLIbsZH+zdhC0PYLDU+YjC9gIZ6Es5PW+hlU6hFP/7VcHyw1 VWFEP1ZUOU6E1OM6LcMrQqfb4/hO5Iuzyfk62VODb4DN1eRa8LqamWdPSJNAEN6zKyEr LppUh8by+s2kTbeA+v14WmHCedvtOZjE8JkTylLTgZ0au36fXa6URPOgJ58FSpnNepq3 Vmzg== X-Gm-Message-State: AKaTC03+10y/MtaM/8Wx8H1FrNoiZFEmSu6xR61+Jog/LtYPcbCMXfoyTm8Vu2r7UbbsIPvSK1k= X-Received: by 10.99.196.70 with SMTP id m6mr76831033pgg.118.1480652130666; Thu, 01 Dec 2016 20:15:30 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id u78sm3402349pfa.53.2016.12.01.20.15.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Dec 2016 20:15:30 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Fri, 2 Dec 2016 12:13:10 +0800 Message-Id: <1480652017-31676-18-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480652017-31676-1-git-send-email-heyi.guo@linaro.org> References: <1480652017-31676-1-git-send-email-heyi.guo@linaro.org> Cc: sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v5 17/44] D02/D03/D05: Support Spd mirror mode X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Add Spd mirror mode related registers definition, this is used by memoryinit binary code,base this definition it could support spd mirror mode to have diffrent configuration about MR register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index c24930f..2663cad 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -161,6 +161,7 @@ typedef struct _DDR_DIMM{ UINT16 DimmSize; UINT16 DimmSpeed; UINT32 RankSize; + UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode struct DDR_RANK Rank[MAX_RANK_DIMM]; }DDR_DIMM; @@ -337,6 +338,7 @@ typedef struct _MEMORY{ UINT8 Config0; UINT8 marginTest; UINT8 Config1[5]; + UINT8 ErrorBypass; //register of spd mirror mode UINT32 Config2; }MEMORY; @@ -789,6 +791,8 @@ struct ODT_ACTIVE_STRUCT { #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK +#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM +#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM #define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte #define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte