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[54.225.227.206]) by mx.google.com with ESMTP id q64si2045261qtd.99.2016.12.01.20.38.52; Thu, 01 Dec 2016 20:38:52 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 363FA60871; Fri, 2 Dec 2016 04:38:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 91B2E634C0; Fri, 2 Dec 2016 04:22:28 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 3603B60EE4; Fri, 2 Dec 2016 04:21:54 +0000 (UTC) Received: from mail-pf0-f174.google.com (mail-pf0-f174.google.com [209.85.192.174]) by lists.linaro.org (Postfix) with ESMTPS id 7C05262F1C for ; Fri, 2 Dec 2016 04:16:11 +0000 (UTC) Received: by mail-pf0-f174.google.com with SMTP id d2so50187779pfd.0 for ; Thu, 01 Dec 2016 20:16:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=r0ObqegPcKsa/1UubLQoWUXM0Z9W3afvZnRndPbMN9g=; b=Cmd31C8mZ8aB0mDBPuAx6Zww0lGXosDyWYIIpiqa1HMIqisiIu4iiFz9zhux5dWZ5l Fw+yKsCfrJhH8yq78cMbbUJUO11iC3MnwPvEYxXRuBzUEOGe5XNhJAFhP9BZ9p/0DFOI X/el73hFcxY2kNgM3B8ZEhmcxFeeHyh+/zUtzG8HDafDeZwDbpl4HD35Qu8eMjpNA+Um DWchvPRLLFCyHqK3bg5GrXgFpote0mf8Xr8L4sDMLwGnWeYlqiIxiRiebHA0P7P8dG5u DpefKeuSQQrflZ0mFaYssicsIC2Fxs21j374542IYGobneESGN62c9SaTr2FXxZzfeLs OT5w== X-Gm-Message-State: AKaTC03B2sA5bIggE9z5yARIjTtpQb0c4vpzqBdmN8ikFTA51qXWHTtF0wYjJ3OdJCfnNgNNZEo= X-Received: by 10.99.146.76 with SMTP id s12mr75180994pgn.8.1480652170765; Thu, 01 Dec 2016 20:16:10 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id u78sm3402349pfa.53.2016.12.01.20.16.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 01 Dec 2016 20:16:10 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Fri, 2 Dec 2016 12:13:29 +0800 Message-Id: <1480652017-31676-37-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480652017-31676-1-git-send-email-heyi.guo@linaro.org> References: <1480652017-31676-1-git-send-email-heyi.guo@linaro.org> Cc: Xiang Chen , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v5 36/44] D03/ACPI: support 50MHZ and 66MHZ boards in acpi mode X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" 1. Check the value of register(0xD000E014) to decide whether this is 50MHZ or 66MHZ board attached. Configure register PHY_CTRL to support 50MHZ or 66MHZ. Default Configure of PHY_CTRL is the configure of 50MHZ, if 66MHZ board attached, change the value of PHY_CTRL. 2. D03 have 66M and 50M two types boards, they refer the different reference clock, set the PCD to 0 so that the code will read frequency from register and be adapted to 66M and 50M boards, so also update FVMAIN_SEC binary to adapt different configuration about 50MHZ and 66MHZ boards. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Xiang Chen Reviewed-by: Graeme Gregory Reviewed-by: Leif Lindholm --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl | 122 ++++++++++++++++++++- Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv | Bin 262144 -> 262144 bytes Platforms/Hisilicon/D03/D03.dsc | 4 +- 3 files changed, 124 insertions(+), 2 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl index e19ea18..9944a50 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Sas.asl @@ -80,6 +80,32 @@ Scope(_SB) STS, 32, } + OperationRegion (PHYS, SystemMemory, 0xC3002000, 0x2000) + Field (PHYS, DWordAcc, NoLock, Preserve) { + Offset (0x0014), + PHY0, 32, + Offset (0x0414), + PHY1, 32, + Offset (0x0814), + PHY2, 32, + Offset (0x0c14), + PHY3, 32, + Offset (0x1014), + PHY4, 32, + Offset (0x1414), + PHY5, 32, + Offset (0x1814), + PHY6, 32, + Offset (0x1c14), + PHY7, 32, + } + + OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) + Field (SYSR, DWordAcc, NoLock, Preserve) { + Offset (0xe014), + DIE4, 32, + } + Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST) @@ -88,6 +114,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1) + Store(DIE4, local0) + If (LEqual (local0, 0)) { + /* 66MHZ */ + Store(0x0199B694, Local1) + Store(Local1, PHY0) + Store(Local1, PHY1) + Store(Local1, PHY2) + Store(Local1, PHY3) + Store(Local1, PHY4) + Store(Local1, PHY5) + Store(Local1, PHY6) + Store(Local1, PHY7) + } } } @@ -157,6 +196,32 @@ Scope(_SB) STS, 32, } + OperationRegion (PHYS, SystemMemory, 0xA2002000, 0x2000) + Field (PHYS, DWordAcc, NoLock, Preserve) { + Offset (0x0014), + PHY0, 32, + Offset (0x0414), + PHY1, 32, + Offset (0x0814), + PHY2, 32, + Offset (0x0c14), + PHY3, 32, + Offset (0x1014), + PHY4, 32, + Offset (0x1414), + PHY5, 32, + Offset (0x1814), + PHY6, 32, + Offset (0x1c14), + PHY7, 32, + } + + OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) + Field (SYSR, DWordAcc, NoLock, Preserve) { + Offset (0xe014), + DIE4, 32, + } + Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST) @@ -165,6 +230,19 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1) + Store(DIE4, local0) + If (LEqual (local0, 0)) { + /* 66MHZ */ + Store(0x0199B694, Local1) + Store(Local1, PHY0) + Store(Local1, PHY1) + Store(Local1, PHY2) + Store(Local1, PHY3) + Store(Local1, PHY4) + Store(Local1, PHY5) + Store(Local1, PHY6) + Store(Local1, PHY7) + } } } @@ -216,7 +294,7 @@ Scope(_SB) Package () {"interrupt-parent",Package() {\_SB.MBI2}}, Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}}, Package () {"queue-count", 16}, - Package () {"phy-count", 8}, + Package () {"phy-count", 9}, } }) @@ -233,6 +311,34 @@ Scope(_SB) STS, 32, } + OperationRegion (PHYS, SystemMemory, 0xA3002000, 0x2400) + Field (PHYS, DWordAcc, NoLock, Preserve) { + Offset (0x0014), + PHY0, 32, + Offset (0x0414), + PHY1, 32, + Offset (0x0814), + PHY2, 32, + Offset (0x0c14), + PHY3, 32, + Offset (0x1014), + PHY4, 32, + Offset (0x1414), + PHY5, 32, + Offset (0x1814), + PHY6, 32, + Offset (0x1c14), + PHY7, 32, + offset (0x2014), + PHY8, 32, + } + + OperationRegion (SYSR, SystemMemory, 0xD0000000, 0x10000) + Field (SYSR, DWordAcc, NoLock, Preserve) { + Offset (0xe014), + DIE4, 32, + } + Method (_RST, 0x0, Serialized) { Store(0x7ffff, RST) @@ -241,6 +347,20 @@ Scope(_SB) Store(0x7ffff, DRST) Store(0x7ffff, CLK) Sleep(1) + Store(DIE4, local0) + If (LEqual (local0, 0)) { + /* 66MHZ */ + Store(0x0199B694, Local1) + Store(Local1, PHY0) + Store(Local1, PHY1) + Store(Local1, PHY2) + Store(Local1, PHY3) + Store(Local1, PHY4) + Store(Local1, PHY5) + Store(Local1, PHY6) + Store(Local1, PHY7) + Store(Local1, PHY8) + } } } diff --git a/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv b/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv index 1050b92..1830a6a 100644 Binary files a/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv and b/Platforms/Hisilicon/Binary/D03/Sec/FVMAIN_SEC.Fv differ diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index aa085da..850b16b 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -218,7 +218,9 @@ # # ARM Architectual Timer Frequency # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|66000000 + # Set it to 0 so that the code will read frequence from register and be + # adapted to 66M and 50M boards + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0 gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE