From patchwork Tue Feb 28 15:11:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 94635 Delivered-To: patch@linaro.org Received: by 10.140.20.113 with SMTP id 104csp1364368qgi; Tue, 28 Feb 2017 07:13:56 -0800 (PST) X-Received: by 10.200.35.6 with SMTP id a6mr3186904qta.210.1488294836087; Tue, 28 Feb 2017 07:13:56 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id s68si1670123qkf.118.2017.02.28.07.13.55; Tue, 28 Feb 2017 07:13:56 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8B2E5636FE; Tue, 28 Feb 2017 15:13:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id CE857636DE; Tue, 28 Feb 2017 15:12:32 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 43273636EA; Tue, 28 Feb 2017 15:12:26 +0000 (UTC) Received: from mail-wr0-f177.google.com (mail-wr0-f177.google.com [209.85.128.177]) by lists.linaro.org (Postfix) with ESMTPS id 390C0636E5 for ; Tue, 28 Feb 2017 15:11:39 +0000 (UTC) Received: by mail-wr0-f177.google.com with SMTP id g10so10889542wrg.2 for ; Tue, 28 Feb 2017 07:11:39 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=43Ujz+XhbYj6K39qNA6KFJkJIWeS/j5NOgEep48o88k=; b=XklGU+8GCwps6H+vLb7W6bfdprdcCTaP6YgTC4yXOMm8Iq3teWjpScJR6REcDsnobY +MTTxmnS/65pnsMdoqIulb0Ypr1poh4L9rOB6RMxQBRmKcvgBylyqxzFWGsij7e2ZB+9 cQ6K9jLDVrzjO02jFzwBN44kf2CQmqZZNFEFcEKdjsylcYFUkII2CvpGJ9AA7p5gmYyL qlf/Z22Yy/ISUd6z4gjS3TL7xsFl6zJXPIjaLNQEEIianX4eNYA85s8lb6gl/z1SrXtg U/7eU/qDtT9njwwdqJhLwxvHJADQ+mEa2JFpe1vE3MBZKVt6okkHgIsAB1tGfPAnqEVt mtZA== X-Gm-Message-State: AMke39ls2PkfZbmE4XblL6Ig19d2Iz1wifGbZprOi7De9Mumex9JA4h0s4d44ZSV7FFtYOxUq7w= X-Received: by 10.223.138.250 with SMTP id z55mr3032485wrz.130.1488294698294; Tue, 28 Feb 2017 07:11:38 -0800 (PST) Received: from localhost.localdomain ([105.149.201.216]) by smtp.gmail.com with ESMTPSA id q1sm3086698wmd.6.2017.02.28.07.11.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Feb 2017 07:11:37 -0800 (PST) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org, leif.lindholm@linaro.org, alan@softiron.co.uk Date: Tue, 28 Feb 2017 15:11:19 +0000 Message-Id: <1488294680-1884-4-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> References: <1488294680-1884-1-git-send-email-ard.biesheuvel@linaro.org> Subject: [Linaro-uefi] [PATCH v2 3/4] Platforms/AMD/Overdrive: enable strict memory permission policy X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Implement a strict separation between writable and executable memory, by enabling the new core features that - map PE/COFF code and data sections with either executable or writable permissions, but never both; - map all other regions with the XN attributes set. Note that the former requires 4 KB section alignment, which is not the default when using the tiny code model, so set the section alignment explicitly both for DEBUG and RELEASE builds. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index a236836db691..dcab8fb43cec 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -273,6 +273,9 @@ DEFINE DO_KCS = 1 [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 +[BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION] + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1000 + ################################################################################ # # Pcd Section - list of all EDK II PCD Entries defined by this Platform @@ -440,6 +443,19 @@ DEFINE DO_KCS = 1 ## ACPI (no tables < 4GB) gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >= 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM and OS + # reserved ones, with the exception of LoaderData regions, of which OS loaders + # (i.e., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 + !if $(DO_PSCI) gAmdStyxTokenSpaceGuid.PcdPsciOsSupport|TRUE !else