From patchwork Mon Mar 20 13:11:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95540 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp937968qgd; Mon, 20 Mar 2017 06:19:35 -0700 (PDT) X-Received: by 10.36.94.206 with SMTP id h197mr9224161itb.27.1490015975506; Mon, 20 Mar 2017 06:19:35 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id 62si17668939ioz.249.2017.03.20.06.19.35; Mon, 20 Mar 2017 06:19:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id CF68B6086C; Mon, 20 Mar 2017 13:19:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 2900863EA2; Mon, 20 Mar 2017 13:16:59 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 6C01D60747; Mon, 20 Mar 2017 13:16:39 +0000 (UTC) Received: from mail-pg0-f47.google.com (mail-pg0-f47.google.com [74.125.83.47]) by lists.linaro.org (Postfix) with ESMTPS id 4CC9863E7A for ; Mon, 20 Mar 2017 13:15:22 +0000 (UTC) Received: by mail-pg0-f47.google.com with SMTP id n190so77332832pga.0 for ; Mon, 20 Mar 2017 06:15:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qoTwTcPYiWS7ZYKwwq9oNhp0Pk/wBtt8O7//z8hNlZ4=; b=lu67deqwC80HSz1G4sMOFtAkCHbS+CJYwxTVPbbgan6d7pmXYAj6DTVwMpfvaBsdcr 7Q1nAYp8HVUwM6TsNtjjK2LtV6fu1gC/NkVntnxnYzuJZV9K++67ottUOFGZfekp0xrx rrBH6R3OacdTeP6yjRuQhzPw617sglWmG7gdxknby7jQGH5GEBXvCWsOGEpZoPvRj8/O 2/fjUMdgDzbQzbHJj8/QW6UwqVcnP3IC5j02BjuO/uXnDtnCQ4KbACs2O3LR7nYVmG/f zmwUCppkC0FiSEnS/67G4wzJzpMC1xqGG+S7mxUBLsG7FUE4XTwf+BY7YVU1ogCdOQNC t1jA== X-Gm-Message-State: AFeK/H15f/V25qoEMFbYkPT0rAGG9bpcz2GW6pHzScawOYFWVUGOtSIdsmPz+d48RnY49bj7zOM= X-Received: by 10.84.233.205 with SMTP id m13mr13770035pln.49.1490015721361; Mon, 20 Mar 2017 06:15:21 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:20 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:16 +0800 Message-Id: <1490015485-53685-13-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 12/21] Hisilicon/D05: support the compatibility of kernel PCIe driver X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" As the PCIe driver is updated in kernel 4.10, and it will read the PCIe resource in the PCIe device, so the resource description should also be put into the Device(PCIx). 1. add _OSC support 2. put the pcie resource description into the Device(PCIx), in order to compatible with kernel 4.10 PCIe driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Signed-off-by: Yi Li Signed-off-by: Chenhui Sun --- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 641 ++++++++++++++++----- 1 file changed, 508 insertions(+), 133 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index f9b4722..deca155 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -40,6 +40,49 @@ Scope(_SB) } } +/* + See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 +*/ +#define PCI_OSC_SUPPORT() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Do not allow native PME, AER */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x10,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + // 1P NA PCIe2 Device (PCI2) { @@ -89,17 +132,43 @@ Scope(_SB) Device (RES2) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) + Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) //host bridge register space }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (0xf) } - } // Device(PCI2) + + Device (RES2) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x2) // Unique ID + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) //host bridge register space + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + Device (R1NA) // reserve 1p NA ECAM resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87] + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + // 1p NB PCIe0 Device (PCI4) { @@ -149,30 +218,55 @@ Scope(_SB) Device (RES4) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a0090000, // Min Base Address - 0x8a009ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0090000, // Min Base Address + 0x8a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } - } // Device(PCI4) + Device (RES4) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x4) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0090000, // Min Base Address + 0x8a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } + // 1P NB PCI1 Device (PCI5) { @@ -219,31 +313,57 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RES5) + Device (RES5) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0200000, // Min Base Address + 0x8a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() + Method (_STA, 0x0, NotSerialized) { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a0200000, // Min Base Address - 0x8a020ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) + Return (RBYV()) } + } // Device(PCI5) + + Device (RES5) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x5) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0200000, // Min Base Address + 0x8a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } - } // Device(PCI5) + } // 1P NB PCIe2 Device (PCI6) @@ -291,31 +411,58 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RES6) + Device (RES6) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00a0000, // Min Base Address + 0x8a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() + Method (_STA, 0x0, NotSerialized) { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a00a0000, // Min Base Address - 0x8a00affff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) + Return (RBYV()) } + } // Device(PCI6) + + Device (RES6) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x6) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00a0000, // Min Base Address + 0x8a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } - } // Device(PCI6) + } + // 1P NB PCIe3 Device (PCI7) { @@ -362,31 +509,120 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RES7) + Device (RES7) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00b0000, // Min Base Address + 0x8a00bffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() + Method (_STA, 0x0, NotSerialized) { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a00b0000, // Min Base Address - 0x8a00bffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) + Return (RBYV()) } + } // Device(PCI7) + Device (RES7) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x7) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00b0000, // Min Base Address + 0x8a00bffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } - } // Device(PCI7) + } + + Device (R1NB) // reserve 1p NB ECAM resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //ECAM space for [bus 88-8f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a8800000, // Min Base Address + 0x8a8ffffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + QwordMemory ( //ECAM space for [bus 0-7] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8b0000000, // Min Base Address + 0x8b07fffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + QwordMemory ( //ECAM space for [bus c0-c7] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8ac000000, // Min Base Address + 0x8ac7fffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + QwordMemory ( //ECAM space for [bus 90-97] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8b9000000, // Min Base Address + 0x8b97fffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } + // 2P NA PCIe2 Device (PCIa) { @@ -433,31 +669,82 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RESa) + Device (RESa) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x600a00a0000, // Min Base Address + 0x600a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() + Method (_STA, 0x0, NotSerialized) { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x600a00a0000, // Min Base Address - 0x600a00affff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) + Return (0xf) } + } // Device(PCIa) + + Device (RESa) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0xa) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x600a00a0000, // Min Base Address + 0x600a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) Method (_STA, 0x0, NotSerialized) { Return (0xf) } - } // Device(PCIa) + } + + Device (R2NA) //reserve for 2p NA ecam resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //ECAM space for [bus 10-1f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x64001000000, // Min Base Address + 0x64001ffffff, // Max Base Address + 0x0, // Translate + 0x1000000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + // 2P NB PCIe0 Device (PCIc) { @@ -504,32 +791,57 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RESc) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x700a0090000, // Min Base Address - 0x700a009ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - } + Device (RESc) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0090000, // Min Base Address + 0x700a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCIc) + Device (RESc) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0xc) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0090000, // Min Base Address + 0x700a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } //2P NB PCIe1 Device (PCId) { @@ -576,30 +888,93 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RESd) + Device (RESd) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ //host bridge register space + QwordMemory ( + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0200000, // Min Base Address + 0x700a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() + Method (_STA, 0x0, NotSerialized) { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x700a0200000, // Min Base Address - 0x700a020ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) + Return (RBYV()) + } + } // Device(PCId) + + Device (RESd) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0xd) // Unique ID + Name (_CRS, ResourceTemplate (){ //host bridge register space + QwordMemory ( + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0200000, // Min Base Address + 0x700a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) } + } + + Device (R2NB) //reserve for 2p NB ecam resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //ECAM space for [bus 20-2f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x74002000000, // Min Base Address + 0x74002ffffff, // Max Base Address + 0x0, // Translate + 0x1000000 // Length + ) + QwordMemory ( //ECAM space for [bus 30-3f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x78003000000, // Min Base Address + 0x78003ffffff, // Max Base Address + 0x0, // Translate + 0x1000000 // Length + ) + }) Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } - } // Device(PCId) + } }