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[54.225.227.206]) by mx.google.com with ESMTP id m76si13316360qki.0.2017.04.10.05.33.16; Mon, 10 Apr 2017 05:33:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 955FD62C74; Mon, 10 Apr 2017 12:33:16 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 5D4D062B8D; Mon, 10 Apr 2017 12:33:14 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E395E62D81; Mon, 10 Apr 2017 12:33:12 +0000 (UTC) Received: from mail-pf0-f175.google.com (mail-pf0-f175.google.com [209.85.192.175]) by lists.linaro.org (Postfix) with ESMTPS id B182060E16 for ; Mon, 10 Apr 2017 12:33:10 +0000 (UTC) Received: by mail-pf0-f175.google.com with SMTP id o126so32762412pfb.3 for ; Mon, 10 Apr 2017 05:33:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t0DhahDXJvMUrrv/csPoYXtDMBnX0dqe+tAN787Idvk=; b=L2fvyyCPHQTEICiMPOGzXc5bpOXfVrkcKgWJiWX1AghjwQx3pnt3H7oUrKdWfb4aXC 0OHvB1IEQkHPyGxw/lMu7kuEMC4U0CFUvnF4TK3pBZ4sKaKe4gDurz7Xa8kHt385qYei fOFwKnt+Qj5MGywkG/I/iVTA1JKfIWgYTV4L5ok3DWau1sCW3l3cFMoSYW0xZrdOCEIX SzkPAwjl6SpMWz93mUNlFtZCjzsJb7oJlXNykt/FFuum90280PxKgkUcsvaAFEMKvZgE 7c78fZY+gLX7ZTPfQJO4kLehI0rv9GB74VyaUwr9Y7QvhsyLRQip7AtB+QTn22FdtYv8 uq6w== X-Gm-Message-State: AFeK/H3F4wyacnOxHnyQZjtvNX6n7e54MH7iirNiEUWcBOgQm7Db3CxZuPCAGc9JQ1Tc4tCOs8Q= X-Received: by 10.99.206.5 with SMTP id y5mr55841108pgf.212.1491827590049; Mon, 10 Apr 2017 05:33:10 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id z21sm24703601pgc.53.2017.04.10.05.33.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 10 Apr 2017 05:33:09 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Mon, 10 Apr 2017 20:29:19 +0800 Message-Id: <1491827361-84793-2-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491827361-84793-1-git-send-email-chenhui.sun@linaro.org> References: <1491827361-84793-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , shaochangliang , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v3 1/3] Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue. X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: shaochangliang The I350 Hilink state is not stable, so we need to modify the rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: shaochangliang Signed-off-by: Heyi Guo Signed-off-by: Yi Li Signed-off-by: Chenhui Sun --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 2 ++ Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 0b5a659..a9b3d74 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -470,6 +470,8 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); Value |= (1 << 20); //bit 20: rxvalid enable RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + RegWrite (PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i * MUX_CFG_STRIDE, \ + CH_RXTX_STATUS_CFG_EN | CH_RXTX_STATUS_CFG); } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 9671c57..9a0f636 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -70,6 +70,10 @@ #define PCS_SDS_CFG_REG 0x204 #define SDS_CFG_STRIDE 0x4 +#define MUX_LOS_ALOS_REG_OFFSET 0x508 +#define MUX_CFG_STRIDE 0x4 +#define CH_RXTX_STATUS_CFG_EN BIT1 +#define CH_RXTX_STATUS_CFG BIT2 #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr))