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[54.225.227.206]) by mx.google.com with ESMTP id n55si9736439qta.8.2017.09.19.07.11.22; Tue, 19 Sep 2017 07:11:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E729D6446E; Tue, 19 Sep 2017 14:11:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id C076C62CE2; Tue, 19 Sep 2017 14:09:47 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id EDD3F62C5C; Tue, 19 Sep 2017 14:05:40 +0000 (UTC) Received: from mail-pf0-f175.google.com (mail-pf0-f175.google.com [209.85.192.175]) by lists.linaro.org (Postfix) with ESMTPS id 06BB562C6C for ; Tue, 19 Sep 2017 14:05:10 +0000 (UTC) Received: by mail-pf0-f175.google.com with SMTP id p87so31651pfj.9 for ; Tue, 19 Sep 2017 07:05:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hPCbigJ/QdT/KTFXNcgaZbW3s6EwIhX2j0rMWgvYJiI=; b=q7h21NFSWrgy3O6EFTSNi0uvU5Uhx+xy4fdtTXoC5gJHJASByhi8fw1GGISP9M+0Q1 LYEqShAT1Fd4giAxZFcCxxtdHtNfOiQDD5P7OxHweqoFualBUnFU3B0/8xEt8p9bXYVb IJMbSB1u2wfjbCCuj+3/qt8DFpqSuRTWtoArt9ZTdcT9t6PcSSgIgdus4tfZ6JyH3pn9 2YxtPIHinXJ5d/C7g/0cmXt8RgQ29GfrxJ1Bzzb8x4/pM7Vu/2Vun0pB4RpOy2Q52Fcy qxuHqKRuAt0kHdaI3CdBelhvsWI+YyipzmgrjYqN8+WvNnSTKkcL7ivWvlVwWy5B8Jdm JSpw== X-Gm-Message-State: AHPjjUjJwUdOC/d1zYNjA//e5r+8Ogmj3b62lU0iyJpAvvlDz9+jmleC nFmj6cacjEs/T9wk6UNpYI/yKPwS X-Google-Smtp-Source: AOwi7QCPeW44CVoV/Lb+bj1GbdB1Mz9XG1H4Bj+hvj/FmG2WcwViUeZzxuXPN8anMM9AWdjQnM/zIg== X-Received: by 10.98.8.81 with SMTP id c78mr1436758pfd.166.1505829909132; Tue, 19 Sep 2017 07:05:09 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:08 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:12 +0800 Message-Id: <1505829398-52214-7-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, Anurup M , guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 06/32] Hisilicon D05: Uncore PMU: Add L3 cache, MN PMU devices and properties X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun 1) The Hisilicon SoC uncore PMU devices like L3 cache, MN etc are probed by djtag. The djtag will have _HID and L3 cache and MN will use _ADR and _CID to identity the hardware version. 2) Use QWordMemory to support 64-bit address of CPU sysctrl. 3) Include UncorePMU asl in Hi1616 Dsdt. Signed-off-by: Anurup M --- .../Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl | 385 +++++++++++++++++++++ .../Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl | 1 + 2 files changed, 386 insertions(+) create mode 100644 Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl new file mode 100644 index 0000000..d2a1432 --- /dev/null +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl @@ -0,0 +1,385 @@ +/** @file + Differentiated System Description Table Fields (DSDT) + + Copyright (c) 2017, ARM Ltd. All rights reserved.
+ Copyright (c) 2017, Hisilicon Limited. All rights reserved.
+ Copyright (c) 2017, Linaro Limited. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/ + +**/ + +Scope(_SB) { + // Djtag for CPU die #1 (scl #1) + Device (DJT0) { + Name (_HID, "HISI0202") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x40010000, // Min Base Address + 0x4001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01} + } + }) + + // L3C Bank 0 for SCL #1 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x01, 0x01}}, + } + }) + } + + // L3C Bank 1 for SCL #1 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x02, 0x01}}, + } + }) + } + + // L3C Bank 2 for SCL #1 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0212") + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x03, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #1 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // MN1 for SCL #1 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0222") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0x21}, + } + }) + } + } + + // Djtag for CPU die #2 (scl #3) + Device (DJT1) { + Name (_HID, "HISI0202") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x60010000, // Min Base Address + 0x6001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x03}, + } + }) + + // L3C Bank 0 for SCL #3 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x01, 0x01}}, + } + }) + } + + // L3C Bank 1 for SCL #3 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x02, 0x01}}, + } + }) + } + + // L3C Bank 2 for SCL #3 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x03, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #3 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // MN1 for SCL #3 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0222") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0x21}, + } + }) + } + } + + // Djtag for CPU die #3 (scl #5) + Device (DJT2) { + Name (_HID, "HISI0202") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x40040010000, // Min Base Address + 0x4004001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x05} + } + }) + + // L3C Bank 0 for SCL #5 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x01, 0x01}}, + } + }) + } + + // L3C Bank 1 for SCL #5 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0212") + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x02, 0x01}}, + } + }) + } + + // L3C Bank 2 for SCL #5 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x03, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #5 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // MN1 for SCL #5 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0222") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0x21}, + } + }) + } + } + + // Djtag for CPU die #4 (scl #7) + Device (DJT3) { + Name (_HID, "HISI0202") // _HID: Hardware ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( // CPU die sysctrl memory region + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x0, // Granularity + 0x40060010000, // Min Base Address + 0x4006001FFFF, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x07} + } + }) + + // L3C Bank 0 for SCL #7 + Device (L3C0) { + Name (_ADR, 0) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x01, 0x01}}, + } + }) + } + + // L3C Bank 1 for SCL #7 + Device (L3C1) { + Name (_ADR, 1) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x02, 0x01}}, + } + }) + } + + // L3C Bank 2 for SCL #7 + Device (L3C2) { + Name (_ADR, 2) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x03, 0x01}}, + } + }) + } + + // L3C Bank 3 for SCL #7 + Device (L3C3) { + Name (_ADR, 3) + Name (_CID, "HISI0212") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", Package () {0x04, 0x01}}, + } + }) + } + + // MN1 for SCL #7 + Device (MN1) { + Name (_ADR, 4) + Name (_CID, "HISI0222") + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,module-id", 0x21}, + } + }) + } + } +} diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl index b4fc538..e4928b6 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl @@ -28,4 +28,5 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI ", "HIP07 ", EFI_ACPI_ARM_O include ("D05Hns.asl") include ("D05Sas.asl") include ("D05Pci.asl") + include ("D05UncorePmu.asl") }