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[54.225.227.206]) by mx.google.com with ESMTP id g128si1764052qkg.434.2017.09.19.07.12.31; Tue, 19 Sep 2017 07:12:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9992D62D0D; Tue, 19 Sep 2017 14:12:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 309C362D11; Tue, 19 Sep 2017 14:09:54 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 59D7D62C62; Tue, 19 Sep 2017 14:05:43 +0000 (UTC) Received: from mail-pf0-f169.google.com (mail-pf0-f169.google.com [209.85.192.169]) by lists.linaro.org (Postfix) with ESMTPS id B024B62C7E for ; Tue, 19 Sep 2017 14:05:12 +0000 (UTC) Received: by mail-pf0-f169.google.com with SMTP id z84so39865pfi.2 for ; Tue, 19 Sep 2017 07:05:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=emmEn9Eq2IaukDQNh6Bryt4Z8rrM5547xXFLnoUNyZI=; b=tTgqk4hjNyv7f+y2bgoPErO5N8xVh/ZV/R53e5V1zzfBQ+2+S1Y+SSr1AiJdEFHGTo gw12pG5fmNByaiRf/SmWquJsW6QnVy0stYWinaixEzEzhyYZc9NGZnJ399W8dT/ZYvvo OraYa//hFq7DzEMcgPBPomchGqSGthklr3yWCN57WM6UIS628NxE5rqvFRrgUfRGJSh+ AuEO2we2flFhaW5K0hxOp1ej3ULOtBiUISh+RC3ot0oSed0R3k/0DpIrszrMiEWzjaD8 yaRclQO+gLG56cpiP6sXvbIcmwb5JbJeOOgXFU3FFee7Reg8oIuxCCFTSUlztxa6Tuc9 bITA== X-Gm-Message-State: AHPjjUgmZ6OCb513AOOJ8P/GfZtuYdfUGlYZ5z+uzsonMPLeT4BaIBaM u7Roj8VEIEwolnJR+1pwgfj/ZeLX X-Google-Smtp-Source: AOwi7QBgpKx+Versg9TxoSGMjV+cJs4tb9od3kVfPjrjeAqAPBvseglUNC9MmqHLHSvJAcIDw4Sktg== X-Received: by 10.84.238.131 with SMTP id v3mr1443589plk.342.1505829911974; Tue, 19 Sep 2017 07:05:11 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:11 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:13 +0800 Message-Id: <1505829398-52214-8-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, zhangjinsong2@huawei.com, Anurup M , guoheyi@huawei.com, Chenhui Sun , wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 07/32] Hisilicon D03: Uncore PMU: Add DDRC PMU device and properties X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Chenhui Sun Use _HID of HISI0231 for DDRC uncore PMU in hi1612. Every CPU die support 2 DDRC channels and each DDRC channel will be represented as a device with _HID and _UID. The device will also support _STA method. Signed-off-by: Anurup M --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl | 137 ++++++++++++++++++++- 1 file changed, 136 insertions(+), 1 deletion(-) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl index 6d07475..96aaaa5 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03UncorePmu.asl @@ -200,5 +200,140 @@ Scope(_SB) { }) } } -} + // DDRC Channel 0 for CPU die #1 (scl #1) + Device (DDR0) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 0) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40348000, // Min Base Address + 0x40348FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01}, + Package () {"hisilicon,ch-id", 0x00}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 1 for CPU die #1 (scl #1) + Device (DDR1) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x40358000, // Min Base Address + 0x40358FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x01}, + Package () {"hisilicon,ch-id", 0x01}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 0 for CPU die #2 (scl #2) + Device (DDR2) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 2) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x60348000, // Min Base Address + 0x60348FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x02}, + Package () {"hisilicon,ch-id", 0x00}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + // DDRC Channel 1 for CPU die #2 (scl #2) + Device (DDR3) { + Name (_HID, "HISI0231") // _HID: Hardware ID + Name (_UID, 3) // _UID: Unique ID + Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings + QWordMemory ( + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x60358000, // Min Base Address + 0x60358FFF, // Max Base Address + 0x0, // Translate + 0x1000 // Length + ) + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"hisilicon,scl-id", 0x02}, + Package () {"hisilicon,ch-id", 0x01}, + } + }) + + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } +}