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[54.225.227.206]) by mx.google.com with ESMTP id i21si1988102qti.429.2017.09.20.08.00.41; Wed, 20 Sep 2017 08:00:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id A2AD760CC6; Wed, 20 Sep 2017 15:00:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id E961860D3A; Wed, 20 Sep 2017 14:57:27 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id AA3A2636AF; Wed, 20 Sep 2017 14:57:23 +0000 (UTC) Received: from mail-pf0-f178.google.com (mail-pf0-f178.google.com [209.85.192.178]) by lists.linaro.org (Postfix) with ESMTPS id 04DC760CE2 for ; Wed, 20 Sep 2017 14:56:09 +0000 (UTC) Received: by mail-pf0-f178.google.com with SMTP id z84so1655093pfi.2 for ; Wed, 20 Sep 2017 07:56:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OumtfoCTZN9MDHzyy9xR1aHMNWThC57ULD4iyGysZ7w=; b=aMcvkOfP3nDYCxSJzyemFHCIDzxHpIvJhVtFsTzNsDReHyZjKU91hJ+qqcsFt4dqYq CT1iJ1ltZvB+74in87J9BD84FIG0n8hccQtmmoZhGrJIkSeBX2afvY05VJtg1m0UVuk2 r9uSdG32+mWf9kOvSSI4YCxUW6p2H5VTtLC9E7b6yESk1qjU+0b5f0X4Vt7thGLielUo Dpou6Z1k4vwa3JvGGUJN4H+loNVbS75SS6bQOJviT6zJItX+WtiaYrqa+JhRXrpkEUau BBLz8wKfK2M1ApKdLJp0i895YnnFmKEPawD28XpuVthYw4T0OQAPu5gox4AQIj/7jQjS lz/Q== X-Gm-Message-State: AHPjjUjEb2p66tL98XK/8qYjj4ZJP0tW3MLGmL+rTDhCcr8AB1hLU5zA TA85OsW8MhWt+gH/dopHkuG3s8CE X-Google-Smtp-Source: AOwi7QCtFP7he20jtMyi2Ao6AGpk8E/exvHLItBjbroyLx9NfTghtZfcLKqSyzQGRXhPnpnHxbUmuQ== X-Received: by 10.98.211.76 with SMTP id q73mr2418257pfg.348.1505919368203; Wed, 20 Sep 2017 07:56:08 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id c7sm9157624pfc.55.2017.09.20.07.56.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Sep 2017 07:56:07 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Wed, 20 Sep 2017 22:48:53 +0800 Message-Id: <1505918938-52550-10-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505918938-52550-1-git-send-email-heyi.guo@linaro.org> References: <1505918938-52550-1-git-send-email-heyi.guo@linaro.org> Cc: guoheyi@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v2 06/11] D05/PCIe: Modify PcieRegionBase of secondary chip X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: huangming On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are 0x20000000 and 0x30000000 based. These addresses overlap with the DDR memory range 0-1G. In this situation, on the inbound direction, our pcie will drop the DDR address access that are located in the pci range window and lead to a dataflow error. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Platform/Hisilicon/D05/D05.dsc | 12 ++++++------ Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index c4f1f24..df37650 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -329,12 +329,12 @@ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xafffffff gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xafffffff gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 @@ -352,9 +352,9 @@ gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000 gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000 gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 79267e5..55c7f50 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -646,10 +646,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x20000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x65000000000, // Translate - 0xd0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer, @@ -766,10 +766,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x30000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x75000000000, // Translate - 0xc0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer,