From patchwork Fri Apr 7 13:28:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 97024 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp285318qgd; Fri, 7 Apr 2017 06:29:28 -0700 (PDT) X-Received: by 10.200.3.46 with SMTP id q46mr43116432qtg.243.1491571768060; Fri, 07 Apr 2017 06:29:28 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id c138si4813357qke.203.2017.04.07.06.29.27; Fri, 07 Apr 2017 06:29:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9EB876366B; Fri, 7 Apr 2017 13:29:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, NORMAL_HTTP_TO_IP, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id BF3E963A98; Fri, 7 Apr 2017 13:29:20 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id B65E4643A6; Fri, 7 Apr 2017 13:29:18 +0000 (UTC) Received: from mail-wr0-f181.google.com (mail-wr0-f181.google.com [209.85.128.181]) by lists.linaro.org (Postfix) with ESMTPS id 2F275643B9 for ; Fri, 7 Apr 2017 13:29:05 +0000 (UTC) Received: by mail-wr0-f181.google.com with SMTP id g19so64099796wrb.0 for ; Fri, 07 Apr 2017 06:29:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VYZV4glYwb2y4/mfCjG3SLuUq/ISD5kjWCg10F2hO2E=; b=lmaBfLHU1Qizlw3otv/oPZd1x3Lzw7cNlX86eRvLSxmbPb9b8F4psGNZZTKEou6Fqb V35RFqbb3d73g9OBtXb3DU8SpLlSUMPbwZnV5CeCW/+YdKjrxYITS7YeWHGoYWt7xRcw PzeZo2G2a2wRAKv0f4y9zk1mLUpQU635aKgaz4Z4oZ2AQCPVdY7hwxLJ4y5qFLpWP3jb amtWylIoqpG92R85vard0PKuwVkzrZdntaiZ4mC6iNW674c4d+9GMr76G2k5jvLeXiv0 +DNKTxcsB9Ctgy6qNdkfeCLOKCqfy5U2xVQ+5LMqugiNhqdIGkDbUKgKhOSQ014iUff+ Horg== X-Gm-Message-State: AN3rC/5Wyx/VZj3C8b8ufddx+85qPFRHC3UDKPBs4UkNZqg8A6HHPYe37xLSOghlLpjETWZTcds= X-Received: by 10.223.170.197 with SMTP id i5mr3867925wrc.159.1491571744124; Fri, 07 Apr 2017 06:29:04 -0700 (PDT) Received: from localhost.localdomain ([196.81.139.226]) by smtp.gmail.com with ESMTPSA id c8sm5993936wrd.57.2017.04.07.06.29.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Apr 2017 06:29:03 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Fri, 7 Apr 2017 14:28:51 +0100 Message-Id: <20170407132851.28513-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170407132851.28513-1-ard.biesheuvel@linaro.org> References: <20170407132851.28513-1-ard.biesheuvel@linaro.org> Cc: alan@softiron.co.uk Subject: [Linaro-uefi] [PATCH 2/2] Platforms/AMD: correct legacy PCI interrupt routing in DTS X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The interrupt map in the PCIe node describes something that resembles the legacy interrupt routing of the first slot only, but applies it to all PCI-PCI bridges, which means the wrong interrupt is reported for devices in slots 2 and 3. Since most devices support MSI, this is not actually a big deal, but it would be nice to fix this nonetheless. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb | Bin 7973 -> 8123 bytes Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts | 20 +++++++++++++++----- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dtb index ba4de560d279d79fde086c6e3f79626bd17a108f..8b538d72a243244cbf0895cc7094a605a1403338 100644 GIT binary patch delta 1674 zcmcIkT}V_x6rQ>3y1#eb|DSfn4Xs^M(GaOnawE_nLZ3qFAwoj7G#3&Kd{9u(mq0v) zZ~ZF0wdxi`8ZHr`4^mG-gkX?KuwhVw522ki_g-7`2EH_KX68HRJAZTU%;d@0#`rsV z>l?u>G=hqpj1bXS;9pOKcOKTdy{;ZGN;09Yka^V;m#f2N;vj zs5<;=Jc@f7l!0)KK!0!o+H57f9Y$;|yce=|FXU_iJ_t2D3?=q5o$4Co2&C*D?7vg4 z7d{m`d@qD$r>;+R9^VHqWxwjPF8?b>!f{MQ_rWcP#-4ZRv41)S<;A=n0fvhDLKCU> zBsEK&)9FkRz|jwJXDs@Hv26t_vk4bu@)eXNyd2Q&jByu?i+NtmYdE`6A2pXDnKR}_ zbJToD1M>(DYhVpQOaUI@6W0Lwlxu)|j%WaViYpW#s>UtT`ikIwI8){_aPi{>A>nT3 zA7R8@%U5B}9YgJBcQu~?ucx_uHJR#4Ub@zPgCgM2KK=&ovF;tb1w)?tz1J@9s`!wd zh80iuK3FO5K3HSEeUM<(cM%)P`M_nx0%%YRcD#l`81)B2beMD_Nz^YVtPPMwYYS@W zRUsjN&G#~V_Xl_%m;)^$dK26Yock{sdV-Xp;lL>{hOXD$QEMo~g45E2hmR&EQKQs_ ze*&q4s9N%VbF-r>DgJ7Oi8oq$i}s+(!3AHZ&CqF)J^fea x>6y&aXG9TMw9IsVw5Lv8~F-Mh0jY;4$P79%#%nh&*X|v@ZWp>4_g2L delta 1741 zcmcIkT}abW6u)<$x-U2PshhdbP^qzHS|cmh2Ps7QW>8Scu(8^lOv%DPBdFKtlm!W? zCG{YgEn~{-}M#kI=qvhXtH$Pt)548jW!2nX)%9QxcN7ghax2QMI<7d3i)E@EA6{8dj(_QP`u>5Ft0eWc>uLU z66&#f`MtEyLtzpQDeKmw9LM!j884GS4a=ddZ+)Q*DjmzFimZ=S^jdUC6{JypDw&K~ zsB}h^S_WnMIM%Z!V@xfRF{?*9@k#iuerTCR3C~8H1b)~&3~NgG2bj@BWNh`?PCg4$ z+Adu8vt~?tKwvayt16)aRCn2$C&V*e>NJ(6%UR^XeQ5u7#lP>`rdt+kNOD zBI8YSFJp!t#*FnWt;4(Kew2wQ1MO?!v#!{3Qt19@laQltIzjuE8wp*cC z(-q@&GMON!t-U3D<3j4WPXCji8=v2o-Xiz>fMH zU@654h^Pkx&PyePoX&y+xTDb_mX4IHP0)r`x*zJ5Scfe6c0s?>$#21gvr$Ap3=OWM z|0P3d0cBV$+z;agt<@u$8Z=npv|?cJ{(~XZr0c>b#AuY&$Y>X}(q9!v+3l`=gAxrd zbwJ(=7b5Yfcz$Uej-KKR+UVy`7@~Q2RCrKiANecu=veCMxWEur%1q}+GU?W4md$y7s871xojtvT7!+L5}vX*d4`{O1_> diff --git a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts index 36474a26c9c6..b462910b3bf0 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts +++ b/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/styx-overdrive.dts @@ -261,11 +261,21 @@ bus-range = <0x0 0x7f>; msi-parent = <0x4>; reg = <0x0 0xf0000000 0x0 0x10000000>; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = <0x1000 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>, - <0x1000 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>, - <0x1000 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>, - <0x1000 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>; + interrupt-map-mask = <0xff00 0x0 0x0 0x7>; + interrupt-map = <0x1100 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x120 0x1>, + <0x1100 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x121 0x1>, + <0x1100 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x122 0x1>, + <0x1100 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x123 0x1>, + + <0x1200 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x124 0x1>, + <0x1200 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x125 0x1>, + <0x1200 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x126 0x1>, + <0x1200 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x127 0x1>, + + <0x1300 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x128 0x1>, + <0x1300 0x0 0x0 0x2 0x1 0x0 0x0 0x0 0x129 0x1>, + <0x1300 0x0 0x0 0x3 0x1 0x0 0x0 0x0 0x12a 0x1>, + <0x1300 0x0 0x0 0x4 0x1 0x0 0x0 0x0 0x12b 0x1>; dma-coherent; dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; ranges = <0x1000000 0x0 0x00000000 0x0 0xefff0000 0x00 0x00010000>, /* I/O Memory (size=64K) */