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[50.57.142.19]) by mx.google.com with ESMTPS id nc1si2055037vec.24.2014.02.14.07.54.14 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 14 Feb 2014 07:54:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WEL3x-000859-R8; Fri, 14 Feb 2014 15:52:25 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WEL3u-00080i-O1 for xen-devel@lists.xensource.com; Fri, 14 Feb 2014 15:52:22 +0000 Received: from [85.158.137.68:21040] by server-14.bemta-3.messagelabs.com id 0F/96-08196-5BB3EF25; Fri, 14 Feb 2014 15:52:21 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-5.tower-31.messagelabs.com!1392393138!691212!2 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6739 invoked from network); 14 Feb 2014 15:52:21 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-5.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 14 Feb 2014 15:52:21 -0000 X-IronPort-AV: E=Sophos;i="4.95,845,1384300800"; d="scan'208";a="100823984" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 14 Feb 2014 15:51:46 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.2.342.4; Fri, 14 Feb 2014 10:51:46 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WEL3E-0004ww-GL; Fri, 14 Feb 2014 15:51:40 +0000 From: Stefano Stabellini To: Date: Fri, 14 Feb 2014 15:51:32 +0000 Message-ID: <1392393098-7351-4-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH-4.5 v2 04/10] xen/arm: set GICH_HCR_UIE if all the LRs are in use X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: On return to guest, if there are no free LRs and we still have more interrupt to inject, set GICH_HCR_UIE so that we are going to receive a maintenance interrupt when no pending interrupts are present in the LR registers. The maintenance interrupt handler won't do anything anymore, but receiving the interrupt is going to cause gic_inject to be called on return to guest that is going to clear the old LRs and inject new interrupts. Signed-off-by: Stefano Stabellini --- Changes in v2: - disable/enable the GICH_HCR_UIE bit in GICH_HCR; - only enable GICH_HCR_UIE if this_cpu(lr_mask) == ((1 << nr_lrs) - 1). --- xen/arch/arm/gic.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index ee383bc..0928aca 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -805,8 +805,15 @@ void gic_inject(void) gic_restore_pending_irqs(current); if (!gic_events_need_delivery()) gic_inject_irq_stop(); - else + else { gic_inject_irq_start(); + } + + if ( !list_empty(¤t->arch.vgic.lr_pending) && + this_cpu(lr_mask) == ((1 << nr_lrs) - 1) ) + GICH[GICH_HCR] |= GICH_HCR_UIE; + else + GICH[GICH_HCR] &= ~GICH_HCR_UIE; } int gic_route_irq_to_guest(struct domain *d, const struct dt_irq *irq,