From patchwork Wed Mar 5 04:46:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 25722 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f71.google.com (mail-oa0-f71.google.com [209.85.219.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 9532220540 for ; Wed, 5 Mar 2014 04:48:17 +0000 (UTC) Received: by mail-oa0-f71.google.com with SMTP id j17sf1831883oag.10 for ; Tue, 04 Mar 2014 20:48:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:cc:subject:precedence:list-id:list-unsubscribe:list-post :list-help:list-subscribe:mime-version:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list :list-archive:content-type:content-transfer-encoding; bh=whzGXCzFiJkMsqkAgYp0AZJJEIroqlqrg/S0aBpEI0w=; b=lb23UKRDx2iu7Sf8nworrhiPGtCHFgE2UsVKQXb7VCBi+udj5UgcndHX9DokVY2cd/ ES0Z4DPcpvxCuPkAt6/lEwI3efgTLtr64kV08IiGcxpa52sVZ2Vko5jb6q3olvX5hUhc 4TjPGvqimz8gRZak+RSxvOSOoK/uR2Kz8/36YlALNHe07lNGWQcNBLTlHIjS8Gil60/8 m6NCDitETonOBy7/m9hXhfDehAXj7e60HM5FXiHuPJWRsPwkRHwtiEnZQwoL1ytkxoYD AVWumNJ3RNxUrLE8yebAQNTt4l7neU7e2SxZrQWxiDrHV2WS3doHC795Q+F+2TLI/+Pi HmSA== X-Gm-Message-State: ALoCoQkiM2oURi97MezwOj5ab8Q9/KUrvRmm74XPGE3RMhlmB0p7DRFuc3Irb9n0WPNuKmQ3PUbY X-Received: by 10.182.17.69 with SMTP id m5mr1535655obd.6.1393994896743; Tue, 04 Mar 2014 20:48:16 -0800 (PST) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.30.8 with SMTP id c8ls130431qgc.56.gmail; Tue, 04 Mar 2014 20:48:16 -0800 (PST) X-Received: by 10.58.204.4 with SMTP id ku4mr43315vec.34.1393994896613; Tue, 04 Mar 2014 20:48:16 -0800 (PST) Received: from mail-ve0-f174.google.com (mail-ve0-f174.google.com [209.85.128.174]) by mx.google.com with ESMTPS id xn9si361494vcb.116.2014.03.04.20.48.16 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 04 Mar 2014 20:48:16 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.174; Received: by mail-ve0-f174.google.com with SMTP id oz11so514293veb.19 for ; Tue, 04 Mar 2014 20:48:16 -0800 (PST) X-Received: by 10.58.37.232 with SMTP id b8mr65875vek.27.1393994896539; Tue, 04 Mar 2014 20:48:16 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.130.193 with SMTP id u1csp176629vcs; Tue, 4 Mar 2014 20:48:16 -0800 (PST) X-Received: by 10.229.119.73 with SMTP id y9mr4352025qcq.18.1393994895842; Tue, 04 Mar 2014 20:48:15 -0800 (PST) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id v2si550038qaf.134.2014.03.04.20.48.15 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 04 Mar 2014 20:48:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WL3jQ-0002w2-TG; Wed, 05 Mar 2014 04:47:00 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WL3jP-0002vh-Q9 for xen-devel@lists.xenproject.org; Wed, 05 Mar 2014 04:47:00 +0000 Received: from [85.158.137.68:10197] by server-14.bemta-3.messagelabs.com id 93/E8-08196-24CA6135; Wed, 05 Mar 2014 04:46:58 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-12.tower-31.messagelabs.com!1393994816!2896414!1 X-Originating-IP: [209.85.160.48] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 27366 invoked from network); 5 Mar 2014 04:46:57 -0000 Received: from mail-pb0-f48.google.com (HELO mail-pb0-f48.google.com) (209.85.160.48) by server-12.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 5 Mar 2014 04:46:57 -0000 Received: by mail-pb0-f48.google.com with SMTP id md12so542166pbc.35 for ; Tue, 04 Mar 2014 20:46:55 -0800 (PST) X-Received: by 10.68.136.133 with SMTP id qa5mr4149115pbb.63.1393994815889; Tue, 04 Mar 2014 20:46:55 -0800 (PST) Received: from localhost.localdomain (z88l218.static.ctm.net. [202.175.88.218]) by mx.google.com with ESMTPSA id vn10sm3154534pbc.21.2014.03.04.20.46.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Mar 2014 20:46:54 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Wed, 5 Mar 2014 12:46:23 +0800 Message-Id: <1393994786-17098-4-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.8.5.3 In-Reply-To: <1393994786-17098-1-git-send-email-julien.grall@linaro.org> References: <1393994786-17098-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v2 3/6] xen/arm32: Introduce lookup_processor_type X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Looking for a specific proc_info structure is already implemented in assembly. Implement lookup_processor_type to avoid duplicate code between C and assembly. This function searches the proc_info_list structure following the processor ID. If the search fail, it will return NULL, otherwise a pointer to this structure for the specific processor. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- xen/arch/arm/arm32/head.S | 57 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 43 insertions(+), 14 deletions(-) diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S index 77f5518..68fb499 100644 --- a/xen/arch/arm/arm32/head.S +++ b/xen/arch/arm/arm32/head.S @@ -198,26 +198,16 @@ skip_bss: PRINT("- Setting up control registers -\r\n") /* Get processor specific proc info into r1 */ - mrc CP32(r0, MIDR) /* r0 := our cpu id */ - ldr r1, = __proc_info_start - add r1, r1, r10 /* r1 := paddr of table (start) */ - ldr r2, = __proc_info_end - add r2, r2, r10 /* r2 := paddr of table (end) */ -1: ldr r3, [r1, #PROCINFO_cpu_mask] - and r4, r0, r3 /* r4 := our cpu id with mask */ - ldr r3, [r1, #PROCINFO_cpu_val] /* r3 := cpu val in current proc info */ - teq r4, r3 - beq 2f /* Match => exit, or try next proc info */ - add r1, r1, #PROCINFO_sizeof - cmp r1, r2 - blo 1b + bl __lookup_processor_type + teq r1, #0 + bne 1f mov r4, r0 PRINT("- Missing processor info: ") mov r0, r4 bl putn PRINT(" -\r\n") b fail -2: +1: /* Jump to cpu_init */ ldr r1, [r1, #PROCINFO_cpu_init] /* r1 := vaddr(init func) */ @@ -545,6 +535,45 @@ putn: mov pc, lr #endif /* !CONFIG_EARLY_PRINTK */ +/* This provides a C-API version of __lookup_processor_type */ +GLOBAL(lookup_processor_type) + stmfd sp!, {r4, r10, lr} + mov r10, #0 /* r10 := offset between virt&phys */ + bl __lookup_processor_type + mov r0, r1 + ldmfd sp!, {r4, r10, pc} + +/* Read processor ID register (CP#15, CR0), and Look up in the linker-built + * supported processor list. Note that we can't use the absolute addresses for + * the __proc_info lists since we aren't running with the MMU on (and therefore, + * we are not in correct address space). We have to calculate the offset. + * + * r10: offset between virt&phys + * + * Returns: + * r0: CPUID + * r1: proc_info pointer + * Clobbers r2-r4 + */ +__lookup_processor_type: + mrc CP32(r0, MIDR) /* r0 := our cpu id */ + ldr r1, = __proc_info_start + add r1, r1, r10 /* r1 := paddr of table (start) */ + ldr r2, = __proc_info_end + add r2, r2, r10 /* r2 := paddr of table (end) */ +1: ldr r3, [r1, #PROCINFO_cpu_mask] + and r4, r0, r3 /* r4 := our cpu id with mask */ + ldr r3, [r1, #PROCINFO_cpu_val] /* r3 := cpu val in current proc info */ + teq r4, r3 + beq 2f /* Match => exit, or try next proc info */ + add r1, r1, #PROCINFO_sizeof + cmp r1, r2 + blo 1b + /* We failed to find the proc_info, return NULL */ + mov r1, #0 +2: + mov pc, lr + /* * Local variables: * mode: ASM