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[50.57.142.19]) by mx.google.com with ESMTPS id sh5si1766456vdc.86.2014.03.17.06.53.24 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 17 Mar 2014 06:53:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WPXy3-00014R-49; Mon, 17 Mar 2014 13:52:39 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WPXy0-00012N-TS for xen-devel@lists.xen.org; Mon, 17 Mar 2014 13:52:37 +0000 Received: from [85.158.143.35:11145] by server-1.bemta-4.messagelabs.com id 25/26-09853-42EF6235; Mon, 17 Mar 2014 13:52:36 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-13.tower-21.messagelabs.com!1395064353!2634464!3 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 1983 invoked from network); 17 Mar 2014 13:52:35 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-13.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 17 Mar 2014 13:52:35 -0000 X-IronPort-AV: E=Sophos;i="4.97,670,1389744000"; d="scan'208";a="112110139" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 17 Mar 2014 13:52:32 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Mon, 17 Mar 2014 09:52:32 -0400 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1WPXxw-0000jH-5O; Mon, 17 Mar 2014 13:52:32 +0000 From: Ian Campbell To: Date: Mon, 17 Mar 2014 13:52:30 +0000 Message-ID: <1395064352-2128-2-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1395064315.18221.26.camel@kazak.uk.xensource.com> References: <1395064315.18221.26.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH 2/4] xen: arm: flush TLB on all CPUs when setting or clearing fixmaps X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: These mappings are global and therefore need flushing on all processors. Add flush_all_xen_data_tlb_range_va which accomplishes this. Signed-off-by: Ian Campbell --- xen/arch/arm/mm.c | 4 ++-- xen/include/asm-arm/arm32/page.h | 19 +++++++++++++++++++ xen/include/asm-arm/arm64/page.h | 19 +++++++++++++++++++ 3 files changed, 40 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index fb1bbf2..b7a8df0 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -217,7 +217,7 @@ void set_fixmap(unsigned map, unsigned long mfn, unsigned attributes) pte.pt.ai = attributes; pte.pt.xn = 1; write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte); - flush_xen_data_tlb_local_range_va(FIXMAP_ADDR(map), PAGE_SIZE); + flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE); } /* Remove a mapping from a fixmap entry */ @@ -225,7 +225,7 @@ void clear_fixmap(unsigned map) { lpae_t pte = {0}; write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte); - flush_xen_data_tlb_local_range_va(FIXMAP_ADDR(map), PAGE_SIZE); + flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE); } #ifdef CONFIG_DOMAIN_PAGE diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index daa4931..27027d8 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -82,6 +82,25 @@ static inline void flush_xen_data_tlb_local_range_va(unsigned long va, isb(); } +/* + * Flush a range of VA's hypervisor mappings from the data TLB on all + * processors in the inner-shareable domain. This is not sufficient + * when changing code mappings or for self modifying code. + */ +static inline void flush_xen_data_tlb_range_va(unsigned long va, + unsigned long size) +{ + unsigned long end = va + size; + dsb(); /* Ensure preceding are visible */ + while ( va < end ) { + asm volatile(STORE_CP32(0, TLBIMVAHIS) + : : "r" (va) : "memory"); + va += PAGE_SIZE; + } + dsb(); /* Ensure completion of the TLB flush */ + isb(); +} + /* Ask the MMU to translate a VA for us */ static inline uint64_t __va_to_par(vaddr_t va) { diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 9bea476..61a3e6c 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -74,6 +74,25 @@ static inline void flush_xen_data_tlb_local_range_va(unsigned long va, isb(); } +/* + * Flush a range of VA's hypervisor mappings from the data TLB of all + * processors in the inner-shareable domain. This is not sufficient + * when changing code mappings or for self modifying code. + */ +static inline void flush_xen_data_tlb_range_va(unsigned long va, + unsigned long size) +{ + unsigned long end = va + size; + dsb(); /* Ensure preceding are visible */ + while ( va < end ) { + asm volatile("tlbi vae2is, %0;" + : : "r" (va>>PAGE_SHIFT) : "memory"); + va += PAGE_SIZE; + } + dsb(); /* Ensure completion of the TLB flush */ + isb(); +} + /* Ask the MMU to translate a VA for us */ static inline uint64_t __va_to_par(vaddr_t va) {