From patchwork Thu Mar 20 15:45:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Campbell X-Patchwork-Id: 26717 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-yk0-f199.google.com (mail-yk0-f199.google.com [209.85.160.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id D59C620534 for ; Thu, 20 Mar 2014 15:47:33 +0000 (UTC) Received: by mail-yk0-f199.google.com with SMTP id 200sf5459881ykr.2 for ; Thu, 20 Mar 2014 08:47:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-post:list-help:list-subscribe:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:list-archive:content-type:content-transfer-encoding; bh=A+CfxTDJS6g4e/KsEdlznFKHNJ22t+19Jc9htMAf9go=; b=MefmNzaWraCCLRbkDpnIpVJa1HlE/oT9l4ZOSR940+yK0dzlSG3hRiIg01FSnxt2bN cBpEOq8mY31n4B0OwXxhkWnYCvsxZXoQrBeb/2KpoIn1ZQTdOeU/pZyJgGzzp94OwY+X 43ShdSCL+ooQ4u1rTjz41bHi84zHAzJY4HP3Si/2fArYIwDMSBdLsjHxG1pI9n/hx7FJ 4Wk+jaopEge+ucCszdTfkypaVMhfRW/rP3ZWdepB6W5Opf2qR/30ZdFENoEqFByALso7 3MdvpsWHjUJAWwLuUaaebaObHLchuBr6hidkGKQ/MIQp+ofrxygNKVgFYsasDOA8hzbp S99g== X-Gm-Message-State: ALoCoQmCq4BIu7C/Y/SQSDpMWl7ShNz+uwhTZVtOfL5JuN9hDv7Tr8wQIPyGKM0jsuiO1kVNgXM/ X-Received: by 10.236.45.41 with SMTP id o29mr10340142yhb.13.1395330453618; Thu, 20 Mar 2014 08:47:33 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.37.225 with SMTP id r88ls290990qgr.2.gmail; Thu, 20 Mar 2014 08:47:33 -0700 (PDT) X-Received: by 10.52.230.105 with SMTP id sx9mr29453888vdc.10.1395330453547; Thu, 20 Mar 2014 08:47:33 -0700 (PDT) Received: from mail-vc0-f170.google.com (mail-vc0-f170.google.com [209.85.220.170]) by mx.google.com with ESMTPS id xo2si510454vec.116.2014.03.20.08.47.33 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 20 Mar 2014 08:47:33 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.170; Received: by mail-vc0-f170.google.com with SMTP id hu19so1176808vcb.29 for ; Thu, 20 Mar 2014 08:47:33 -0700 (PDT) X-Received: by 10.52.126.107 with SMTP id mx11mr3584280vdb.41.1395330453408; Thu, 20 Mar 2014 08:47:33 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.78.9 with SMTP id i9csp398555vck; Thu, 20 Mar 2014 08:47:33 -0700 (PDT) X-Received: by 10.220.68.83 with SMTP id u19mr749136vci.52.1395330452722; Thu, 20 Mar 2014 08:47:32 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id fv9si511583vcb.20.2014.03.20.08.47.29 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 20 Mar 2014 08:47:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WQfAc-0004CI-RZ; Thu, 20 Mar 2014 15:46:14 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WQfAb-0004AA-Ee for xen-devel@lists.xen.org; Thu, 20 Mar 2014 15:46:13 +0000 Received: from [85.158.143.35:62242] by server-1.bemta-4.messagelabs.com id BB/DD-09853-44D0B235; Thu, 20 Mar 2014 15:46:12 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-5.tower-21.messagelabs.com!1395330368!3603483!3 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 26331 invoked from network); 20 Mar 2014 15:46:11 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-5.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 20 Mar 2014 15:46:11 -0000 X-IronPort-AV: E=Sophos;i="4.97,695,1389744000"; d="scan'208";a="111935202" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 20 Mar 2014 15:46:08 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Thu, 20 Mar 2014 11:46:06 -0400 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1WQfAU-0006O2-1c; Thu, 20 Mar 2014 15:46:06 +0000 From: Ian Campbell To: Date: Thu, 20 Mar 2014 15:45:53 +0000 Message-ID: <1395330365-9901-5-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1395330336.3104.12.camel@kazak.uk.xensource.com> References: <1395330336.3104.12.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH 05/17] xen: arm32: resync atomics with (almost) v3.14-rc7 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Almost because I omitting aed3a4e "ARM: 7868/1: arm/arm64: remove atomic_clear_mask() ..." which I will apply to both arm32 and arm64 simultaneously in a later patch. This pulls in the following Linux patches: commit f38d999c4d16fc0fce4270374f15fbb2d8713c09 Author: Will Deacon Date: Thu Jul 4 11:43:18 2013 +0100 ARM: atomics: prefetch the destination word for write prior to strex The cost of changing a cacheline from shared to exclusive state can be significant, especially when this is triggered by an exclusive store, since it may result in having to retry the transaction. This patch prefixes our atomic access implementations with pldw instructions (on CPUs which support them) to try and grab the line in exclusive state from the start. Only the barrier-less functions are updated, since memory barriers can limit the usefulness of prefetching data. Acked-by: Nicolas Pitre Signed-off-by: Will Deacon commit 4dcc1cf7316a26e112f5c9fcca531ff98ef44700 Author: Chen Gang Date: Sat Oct 26 15:07:25 2013 +0100 ARM: 7867/1: include: asm: use 'int' instead of 'unsigned long' for 'oldval For atomic_cmpxchg(), the type of 'oldval' need be 'int' to match the type of "*ptr" (used by 'ldrex' instruction) and 'old' (used by 'teq' instruction). Reviewed-by: Will Deacon Signed-off-by: Chen Gang Signed-off-by: Will Deacon Signed-off-by: Russell King Signed-off-by: Ian Campbell --- xen/include/asm-arm/arm32/atomic.h | 6 +++++- xen/include/asm-arm/atomic.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/xen/include/asm-arm/arm32/atomic.h b/xen/include/asm-arm/arm32/atomic.h index 3f024d4..d309f66 100644 --- a/xen/include/asm-arm/arm32/atomic.h +++ b/xen/include/asm-arm/arm32/atomic.h @@ -21,6 +21,7 @@ static inline void atomic_add(int i, atomic_t *v) unsigned long tmp; int result; + prefetchw(&v->counter); __asm__ __volatile__("@ atomic_add\n" "1: ldrex %0, [%3]\n" " add %0, %0, %4\n" @@ -59,6 +60,7 @@ static inline void atomic_sub(int i, atomic_t *v) unsigned long tmp; int result; + prefetchw(&v->counter); __asm__ __volatile__("@ atomic_sub\n" "1: ldrex %0, [%3]\n" " sub %0, %0, %4\n" @@ -94,7 +96,8 @@ static inline int atomic_sub_return(int i, atomic_t *v) static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new) { - unsigned long oldval, res; + int oldval; + unsigned long res; smp_mb(); @@ -118,6 +121,7 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) { unsigned long tmp, tmp2; + prefetchw(addr); __asm__ __volatile__("@ atomic_clear_mask\n" "1: ldrex %0, [%3]\n" " bic %0, %0, %4\n" diff --git a/xen/include/asm-arm/atomic.h b/xen/include/asm-arm/atomic.h index 69c8f3f..2c92de9 100644 --- a/xen/include/asm-arm/atomic.h +++ b/xen/include/asm-arm/atomic.h @@ -2,6 +2,7 @@ #define __ARCH_ARM_ATOMIC__ #include +#include #include #define build_atomic_read(name, size, width, type, reg)\