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[50.57.142.19]) by mx.google.com with ESMTPS id 6si835563qav.136.2014.04.02.07.15.00 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 02 Apr 2014 07:15:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVLug-0000H5-CH; Wed, 02 Apr 2014 14:13:10 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVLue-0000Gp-NP for xen-devel@lists.xen.org; Wed, 02 Apr 2014 14:13:09 +0000 Received: from [85.158.143.35:64052] by server-3.bemta-4.messagelabs.com id 36/D5-13602-3FA1C335; Wed, 02 Apr 2014 14:13:07 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-16.tower-21.messagelabs.com!1396447985!6392106!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 4419 invoked from network); 2 Apr 2014 14:13:06 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-16.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 2 Apr 2014 14:13:06 -0000 X-IronPort-AV: E=Sophos;i="4.97,780,1389744000"; d="scan'208";a="116106265" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 02 Apr 2014 14:12:53 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.2.342.4; Wed, 2 Apr 2014 10:12:51 -0400 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1WVLuN-00046T-LK; Wed, 02 Apr 2014 14:12:51 +0000 From: Ian Campbell To: Date: Wed, 2 Apr 2014 15:12:51 +0100 Message-ID: <1396447971-27846-3-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1396447908.8667.346.camel@kazak.uk.xensource.com> References: <1396447908.8667.346.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH 3/3] xen: arm32: don't force the compiler to allocate a dummy register X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: TLBIALLH, ICIALLU and BPIALL make no use of their register argument. Instead of making the compiler allocate a dummy register just hardcode r0, there is no need to represent this in the inline asm since the register is neither clobbered nor used in any way. Signed-off-by: Ian Campbell Acked-by: Julien Grall --- xen/include/asm-arm/arm32/page.h | 14 ++++++-------- xen/include/asm-arm/arm32/processor.h | 4 ++++ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index 2b2bbe6..1a49d59 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -37,15 +37,14 @@ static inline void write_pte(lpae_t *p, lpae_t pte) */ static inline void flush_xen_text_tlb_local(void) { - register unsigned long r0 asm ("r0"); asm volatile ( "isb;" /* Ensure synchronization with previous changes to text */ - STORE_CP32(0, TLBIALLH) /* Flush hypervisor TLB */ - STORE_CP32(0, ICIALLU) /* Flush I-cache */ - STORE_CP32(0, BPIALL) /* Flush branch predictor */ + CMD_CP32(TLBIALLH) /* Flush hypervisor TLB */ + CMD_CP32(ICIALLU) /* Flush I-cache */ + CMD_CP32(BPIALL) /* Flush branch predictor */ "dsb;" /* Ensure completion of TLB+BP flush */ "isb;" - : : "r" (r0) /*dummy*/ : "memory"); + : : : "memory"); } /* @@ -55,12 +54,11 @@ static inline void flush_xen_text_tlb_local(void) */ static inline void flush_xen_data_tlb_local(void) { - register unsigned long r0 asm ("r0"); asm volatile("dsb;" /* Ensure preceding are visible */ - STORE_CP32(0, TLBIALLH) + CMD_CP32(TLBIALLH) "dsb;" /* Ensure completion of the TLB flush */ "isb;" - : : "r" (r0) /* dummy */: "memory"); + : : : "memory"); } /* diff --git a/xen/include/asm-arm/arm32/processor.h b/xen/include/asm-arm/arm32/processor.h index 8a35cee..f41644d 100644 --- a/xen/include/asm-arm/arm32/processor.h +++ b/xen/include/asm-arm/arm32/processor.h @@ -69,6 +69,10 @@ struct cpu_user_regs #define LOAD_CP64(r, name...) "mrrc " __stringify(CP64(%r, %H##r, name)) ";" #define STORE_CP64(r, name...) "mcrr " __stringify(CP64(%r, %H##r, name)) ";" +/* Issue a CP operation which takes no argument, + * uses r0 as a placeholder register. */ +#define CMD_CP32(name...) "mcr " __stringify(CP32(r0, name)) ";" + #ifndef __ASSEMBLY__ /* C wrappers */