From patchwork Thu Apr 3 08:59:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Campbell X-Patchwork-Id: 27668 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-we0-f197.google.com (mail-we0-f197.google.com [74.125.82.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E6F6F20490 for ; Thu, 3 Apr 2014 09:02:01 +0000 (UTC) Received: by mail-we0-f197.google.com with SMTP id w62sf1270729wes.0 for ; Thu, 03 Apr 2014 02:02:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-post:list-help:list-subscribe:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:list-archive:content-type:content-transfer-encoding; bh=l2pkUXZhiiZtOj/kY9hmJQ35Mz9jGNNPXE4HcoazOJI=; b=ZDhecLEhg3Nf/YdloqbZkvtJTclNdKxwuoj7t7dVkq9Sh2u71t3x3sYy9OSfhHYnJR yQzSvppBPMsKQoZVZtsLvsfaNxohjvT8/oRJe/mAykbL1dDIJWfQ9ANw5lUUPijcaI16 7U2remly9FGl2l7F+37XDBZ1RdDXwy8vwiHQQMLYbg4q3UlC5KjUjprXAl50G4/t2MMF 0LlTetCogyJzoFyVKSXEWaYJrJIFskFAnIlUMWZnBDY/tRpaNL+l8v1BCA+3jOHjb1PB ymd/P/AHVvI1u3AQTwq8otXDkXm1C10WC5oZNtQCi6vMoFVaC5YT121g5M1/MN5LqzSm wg7Q== X-Gm-Message-State: ALoCoQkEk3X63hmnJUohawhqNCvDlTfsCGU+EZYjnRe9ywyHXHeAP8n2VEj10hP04ccE8wixY9ub X-Received: by 10.15.53.136 with SMTP id r8mr1276701eew.5.1396515720605; Thu, 03 Apr 2014 02:02:00 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.39.133 with SMTP id v5ls543425qgv.23.gmail; Thu, 03 Apr 2014 02:02:00 -0700 (PDT) X-Received: by 10.220.162.6 with SMTP id t6mr1973440vcx.12.1396515720499; Thu, 03 Apr 2014 02:02:00 -0700 (PDT) Received: from mail-ve0-f181.google.com (mail-ve0-f181.google.com [209.85.128.181]) by mx.google.com with ESMTPS id sq9si1134901vdc.125.2014.04.03.02.02.00 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 03 Apr 2014 02:02:00 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.181; Received: by mail-ve0-f181.google.com with SMTP id oy12so45332veb.40 for ; Thu, 03 Apr 2014 02:02:00 -0700 (PDT) X-Received: by 10.220.7.131 with SMTP id d3mr499900vcd.45.1396515720406; Thu, 03 Apr 2014 02:02:00 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.12.8 with SMTP id v8csp11221vcv; Thu, 3 Apr 2014 02:01:57 -0700 (PDT) X-Received: by 10.224.88.131 with SMTP id a3mr6056995qam.54.1396515715995; Thu, 03 Apr 2014 02:01:55 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id 68si1900198qgk.12.2014.04.03.02.01.55 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 03 Apr 2014 02:01:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVdV1-00057J-F8; Thu, 03 Apr 2014 08:59:51 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVdUz-00056t-TK for xen-devel@lists.xen.org; Thu, 03 Apr 2014 08:59:50 +0000 Received: from [85.158.139.211:23624] by server-15.bemta-5.messagelabs.com id ED/49-11079-5032D335; Thu, 03 Apr 2014 08:59:49 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-13.tower-206.messagelabs.com!1396515587!5163521!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23462 invoked from network); 3 Apr 2014 08:59:48 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-13.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 3 Apr 2014 08:59:48 -0000 X-IronPort-AV: E=Sophos;i="4.97,785,1389744000"; d="scan'208";a="116372299" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 03 Apr 2014 08:59:48 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Thu, 3 Apr 2014 04:59:46 -0400 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1WVdUw-0001BA-5c; Thu, 03 Apr 2014 08:59:46 +0000 From: Ian Campbell To: Date: Thu, 3 Apr 2014 09:59:41 +0100 Message-ID: <1396515585-5737-2-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1396515560.4211.33.camel@kazak.uk.xensource.com> References: <1396515560.4211.33.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH v4 2/6] xen: arm: consolidate body of flush_xen_data_tlb_range_va_local X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: This is almost identical on both sub architectures. Signed-off-by: Ian Campbell Acked-by: Julien Grall --- v4: New patch --- xen/include/asm-arm/arm32/page.h | 19 +++---------------- xen/include/asm-arm/arm64/page.h | 19 +++---------------- xen/include/asm-arm/page.h | 18 ++++++++++++++++++ 3 files changed, 24 insertions(+), 32 deletions(-) diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index b0a2025..d839d03 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -63,23 +63,10 @@ static inline void flush_xen_data_tlb_local(void) : : "r" (r0) /* dummy */: "memory"); } -/* - * Flush a range of VA's hypervisor mappings from the data TLB of the - * local processor. This is not sufficient when changing code mappings - * or for self modifying code. - */ -static inline void flush_xen_data_tlb_range_va_local(unsigned long va, - unsigned long size) +/* Flush TLB of local processor for address va. */ +static inline void __flush_xen_data_tlb_one_local(vaddr_t va) { - unsigned long end = va + size; - dsb(sy); /* Ensure preceding are visible */ - while ( va < end ) { - asm volatile(STORE_CP32(0, TLBIMVAH) - : : "r" (va) : "memory"); - va += PAGE_SIZE; - } - dsb(sy); /* Ensure completion of the TLB flush */ - isb(); + asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory"); } /* Ask the MMU to translate a VA for us */ diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 65332a3..897d79b 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -55,23 +55,10 @@ static inline void flush_xen_data_tlb_local(void) : : : "memory"); } -/* - * Flush a range of VA's hypervisor mappings from the data TLB of the - * local processor. This is not sufficient when changing code mappings - * or for self modifying code. - */ -static inline void flush_xen_data_tlb_range_va_local(unsigned long va, - unsigned long size) +/* Flush TLB of local processor for address va. */ +static inline void __flush_xen_data_tlb_one_local(vaddr_t va) { - unsigned long end = va + size; - dsb(sy); /* Ensure preceding are visible */ - while ( va < end ) { - asm volatile("tlbi vae2, %0;" - : : "r" (va>>PAGE_SHIFT) : "memory"); - va += PAGE_SIZE; - } - dsb(sy); /* Ensure completion of the TLB flush */ - isb(); + asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); } /* Ask the MMU to translate a VA for us */ diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index d18ec2a..bbecacf 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -306,6 +306,24 @@ static inline void clean_and_invalidate_xen_dcache_va_range : : "r" (_p), "m" (*_p)); \ } while (0) +/* + * Flush a range of VA's hypervisor mappings from the data TLB of the + * local processor. This is not sufficient when changing code mappings + * or for self modifying code. + */ +static inline void flush_xen_data_tlb_range_va_local(unsigned long va, + unsigned long size) +{ + unsigned long end = va + size; + dsb(sy); /* Ensure preceding are visible */ + while ( va < end ) { + __flush_xen_data_tlb_one_local(va); + va += PAGE_SIZE; + } + dsb(sy); /* Ensure completion of the TLB flush */ + isb(); +} + /* Flush the dcache for an entire page. */ void flush_page_to_ram(unsigned long mfn);