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[50.57.142.19]) by mx.google.com with ESMTPS id tv3si1144731vdc.36.2014.04.03.02.01.55 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 03 Apr 2014 02:01:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVdV2-00058D-E7; Thu, 03 Apr 2014 08:59:52 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVdV0-000571-SX for xen-devel@lists.xen.org; Thu, 03 Apr 2014 08:59:51 +0000 Received: from [85.158.139.211:23752] by server-17.bemta-5.messagelabs.com id D5/44-09046-6032D335; Thu, 03 Apr 2014 08:59:50 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-13.tower-206.messagelabs.com!1396515587!5163521!2 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 23518 invoked from network); 3 Apr 2014 08:59:49 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-13.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 3 Apr 2014 08:59:49 -0000 X-IronPort-AV: E=Sophos;i="4.97,785,1389744000"; d="scan'208";a="116372300" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 03 Apr 2014 08:59:48 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Thu, 3 Apr 2014 04:59:46 -0400 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1WVdUw-0001BA-87; Thu, 03 Apr 2014 08:59:46 +0000 From: Ian Campbell To: Date: Thu, 3 Apr 2014 09:59:42 +0100 Message-ID: <1396515585-5737-3-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1396515560.4211.33.camel@kazak.uk.xensource.com> References: <1396515560.4211.33.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH v4 3/6] xen: arm: flush TLB on all CPUs when setting or clearing fixmaps X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: These mappings are global and therefore need flushing on all processors. Add flush_all_xen_data_tlb_range_va which accomplishes this. Likewise when removing the early mappings Signed-off-by: Ian Campbell Acked-by: Julien Grall --- v4: also make the change in remove_early_mappings consolidatw flush_all_xen_data_tlb_range_va implentation v3: use dsb(sy) not dsb() --- xen/arch/arm/mm.c | 6 +++--- xen/include/asm-arm/arm32/page.h | 7 +++++++ xen/include/asm-arm/arm64/page.h | 7 +++++++ xen/include/asm-arm/page.h | 18 ++++++++++++++++++ 4 files changed, 35 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index d523f77..362bc8d 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -215,7 +215,7 @@ void set_fixmap(unsigned map, unsigned long mfn, unsigned attributes) pte.pt.table = 1; /* 4k mappings always have this bit set */ pte.pt.xn = 1; write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte); - flush_xen_data_tlb_range_va_local(FIXMAP_ADDR(map), PAGE_SIZE); + flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE); } /* Remove a mapping from a fixmap entry */ @@ -223,7 +223,7 @@ void clear_fixmap(unsigned map) { lpae_t pte = {0}; write_pte(xen_fixmap + third_table_offset(FIXMAP_ADDR(map)), pte); - flush_xen_data_tlb_range_va_local(FIXMAP_ADDR(map), PAGE_SIZE); + flush_xen_data_tlb_range_va(FIXMAP_ADDR(map), PAGE_SIZE); } #ifdef CONFIG_DOMAIN_PAGE @@ -403,7 +403,7 @@ void __init remove_early_mappings(void) { lpae_t pte = {0}; write_pte(xen_second + second_table_offset(BOOT_FDT_VIRT_START), pte); - flush_xen_data_tlb_range_va_local(BOOT_FDT_VIRT_START, SECOND_SIZE); + flush_xen_data_tlb_range_va(BOOT_FDT_VIRT_START, SECOND_SIZE); } extern void relocate_xen(uint64_t ttbr, void *src, void *dst, size_t len); diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index d839d03..ead6b97 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -69,6 +69,13 @@ static inline void __flush_xen_data_tlb_one_local(vaddr_t va) asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory"); } +/* Flush TLB of all processors in the inner-shareable domain for + * address va. */ +static inline void __flush_xen_data_tlb_one(vaddr_t va) +{ + asm volatile(STORE_CP32(0, TLBIMVAHIS) : : "r" (va) : "memory"); +} + /* Ask the MMU to translate a VA for us */ static inline uint64_t __va_to_par(vaddr_t va) { diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 897d79b..d7ee2fc 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -61,6 +61,13 @@ static inline void __flush_xen_data_tlb_one_local(vaddr_t va) asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); } +/* Flush TLB of all processors in the inner-shareable domain for + * address va. */ +static inline void __flush_xen_data_tlb_one(vaddr_t va) +{ + asm volatile("tlbi vae2is, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); +} + /* Ask the MMU to translate a VA for us */ static inline uint64_t __va_to_par(vaddr_t va) { diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index bbecacf..a8eeb73 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -324,6 +324,24 @@ static inline void flush_xen_data_tlb_range_va_local(unsigned long va, isb(); } +/* + * Flush a range of VA's hypervisor mappings from the data TLB of all + * processors in the inner-shareable domain. This is not sufficient + * when changing code mappings or for self modifying code. + */ +static inline void flush_xen_data_tlb_range_va(unsigned long va, + unsigned long size) +{ + unsigned long end = va + size; + dsb(sy); /* Ensure preceding are visible */ + while ( va < end ) { + __flush_xen_data_tlb_one(va); + va += PAGE_SIZE; + } + dsb(sy); /* Ensure completion of the TLB flush */ + isb(); +} + /* Flush the dcache for an entire page. */ void flush_page_to_ram(unsigned long mfn);