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[50.57.142.19]) by mx.google.com with ESMTPS id q9si1881171qag.52.2014.04.03.02.01.30 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 03 Apr 2014 02:01:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVdV2-00058a-Ra; Thu, 03 Apr 2014 08:59:52 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVdV0-000576-R4 for xen-devel@lists.xen.org; Thu, 03 Apr 2014 08:59:51 +0000 Received: from [193.109.254.147:2469] by server-11.bemta-14.messagelabs.com id C1/D6-09902-6032D335; Thu, 03 Apr 2014 08:59:50 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1396515587!5961396!2 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 22991 invoked from network); 3 Apr 2014 08:59:49 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-14.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 3 Apr 2014 08:59:49 -0000 X-IronPort-AV: E=Sophos;i="4.97,785,1389744000"; d="scan'208";a="117591370" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 03 Apr 2014 08:59:47 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Thu, 3 Apr 2014 04:59:46 -0400 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1WVdUw-0001BA-EO; Thu, 03 Apr 2014 08:59:46 +0000 From: Ian Campbell To: Date: Thu, 3 Apr 2014 09:59:44 +0100 Message-ID: <1396515585-5737-5-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1396515560.4211.33.camel@kazak.uk.xensource.com> References: <1396515560.4211.33.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH v4 5/6] xen: arm: relax barriers in tlb flushes X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Flushing the local TLB only requires a local barrier. Flushing the TLB of all processors in the inner-shareable domain only requires an inner-shareable barrier. Signed-off-by: Ian Campbell --- v4: new patch --- xen/include/asm-arm/arm32/flushtlb.h | 16 ++++++++-------- xen/include/asm-arm/arm32/page.h | 10 +++++----- xen/include/asm-arm/arm64/flushtlb.h | 16 ++++++++-------- xen/include/asm-arm/arm64/page.h | 10 +++++----- xen/include/asm-arm/page.h | 8 ++++---- 5 files changed, 30 insertions(+), 30 deletions(-) diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h index bbcc82f..621c5d3 100644 --- a/xen/include/asm-arm/arm32/flushtlb.h +++ b/xen/include/asm-arm/arm32/flushtlb.h @@ -4,44 +4,44 @@ /* Flush local TLBs, current VMID only */ static inline void flush_tlb_local(void) { - dsb(sy); + dsb(nsh); WRITE_CP32((uint32_t) 0, TLBIALL); - dsb(sy); + dsb(nsh); isb(); } /* Flush inner shareable TLBs, current VMID only */ static inline void flush_tlb(void) { - dsb(sy); + dsb(ish); WRITE_CP32((uint32_t) 0, TLBIALLIS); - dsb(sy); + dsb(ish); isb(); } /* Flush local TLBs, all VMIDs, non-hypervisor mode */ static inline void flush_tlb_all_local(void) { - dsb(sy); + dsb(nsh); WRITE_CP32((uint32_t) 0, TLBIALLNSNH); - dsb(sy); + dsb(nsh); isb(); } /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ static inline void flush_tlb_all(void) { - dsb(sy); + dsb(ish); WRITE_CP32((uint32_t) 0, TLBIALLNSNHIS); - dsb(sy); + dsb(ish); isb(); } diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index 3f2bdc9..0de3395 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -12,10 +12,10 @@ static inline void write_pte(lpae_t *p, lpae_t pte) { asm volatile ( /* Ensure any writes have completed with the old mappings. */ - "dsb;" + "dsb ish;" /* Safely write the entry (STRD is atomic on CPUs that support LPAE) */ "strd %0, %H0, [%1];" - "dsb;" + "dsb ish;" : : "r" (pte.bits), "r" (p) : "memory"); } @@ -42,7 +42,7 @@ static inline void flush_xen_text_tlb_local(void) CMD_CP32(TLBIALLH) /* Flush hypervisor TLB */ CMD_CP32(ICIALLU) /* Flush I-cache */ CMD_CP32(BPIALL) /* Flush branch predictor */ - "dsb;" /* Ensure completion of TLB+BP flush */ + "dsb nsh;" /* Ensure completion of TLB+BP flush */ "isb;" : : : "memory"); } @@ -54,9 +54,9 @@ static inline void flush_xen_text_tlb_local(void) */ static inline void flush_xen_data_tlb_local(void) { - asm volatile("dsb;" /* Ensure preceding are visible */ + asm volatile("dsb nsh;" /* Ensure preceding are visible */ CMD_CP32(TLBIALLH) - "dsb;" /* Ensure completion of the TLB flush */ + "dsb nsh;" /* Ensure completion of the TLB flush */ "isb;" : : : "memory"); } diff --git a/xen/include/asm-arm/arm64/flushtlb.h b/xen/include/asm-arm/arm64/flushtlb.h index a73df92..ba7059a 100644 --- a/xen/include/asm-arm/arm64/flushtlb.h +++ b/xen/include/asm-arm/arm64/flushtlb.h @@ -5,9 +5,9 @@ static inline void flush_tlb_local(void) { asm volatile( - "dsb sy;" + "dsb nsh;" "tlbi vmalle1;" - "dsb sy;" + "dsb nsh;" "isb;" : : : "memory"); } @@ -16,9 +16,9 @@ static inline void flush_tlb_local(void) static inline void flush_tlb(void) { asm volatile( - "dsb sy;" + "dsb ish;" "tlbi vmalle1is;" - "dsb sy;" + "dsb ish;" "isb;" : : : "memory"); } @@ -27,9 +27,9 @@ static inline void flush_tlb(void) static inline void flush_tlb_all_local(void) { asm volatile( - "dsb sy;" + "dsb nsh;" "tlbi alle1;" - "dsb sy;" + "dsb nsh;" "isb;" : : : "memory"); } @@ -38,9 +38,9 @@ static inline void flush_tlb_all_local(void) static inline void flush_tlb_all(void) { asm volatile( - "dsb sy;" + "dsb ish;" "tlbi alle1is;" - "dsb sy;" + "dsb ish;" "isb;" : : : "memory"); } diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index d7ee2fc..c680f47 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -8,9 +8,9 @@ static inline void write_pte(lpae_t *p, lpae_t pte) { asm volatile ( /* Ensure any writes have completed with the old mappings. */ - "dsb sy;" + "dsb ish;" "str %0, [%1];" /* Write the entry */ - "dsb sy;" + "dsb ish;" : : "r" (pte.bits), "r" (p) : "memory"); } @@ -35,7 +35,7 @@ static inline void flush_xen_text_tlb_local(void) "isb;" /* Ensure synchronization with previous changes to text */ "tlbi alle2;" /* Flush hypervisor TLB */ "ic iallu;" /* Flush I-cache */ - "dsb sy;" /* Ensure completion of TLB flush */ + "dsb nsh;" /* Ensure completion of TLB flush */ "isb;" : : : "memory"); } @@ -48,9 +48,9 @@ static inline void flush_xen_text_tlb_local(void) static inline void flush_xen_data_tlb_local(void) { asm volatile ( - "dsb sy;" /* Ensure visibility of PTE writes */ + "dsb nsh;" /* Ensure visibility of PTE writes */ "tlbi alle2;" /* Flush hypervisor TLB */ - "dsb sy;" /* Ensure completion of TLB flush */ + "dsb nsh;" /* Ensure completion of TLB flush */ "isb;" : : : "memory"); } diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index a8eeb73..a96e40b 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -315,12 +315,12 @@ static inline void flush_xen_data_tlb_range_va_local(unsigned long va, unsigned long size) { unsigned long end = va + size; - dsb(sy); /* Ensure preceding are visible */ + dsb(nsh); /* Ensure preceding are visible */ while ( va < end ) { __flush_xen_data_tlb_one_local(va); va += PAGE_SIZE; } - dsb(sy); /* Ensure completion of the TLB flush */ + dsb(nsh); /* Ensure completion of the TLB flush */ isb(); } @@ -333,12 +333,12 @@ static inline void flush_xen_data_tlb_range_va(unsigned long va, unsigned long size) { unsigned long end = va + size; - dsb(sy); /* Ensure preceding are visible */ + dsb(ish); /* Ensure preceding are visible */ while ( va < end ) { __flush_xen_data_tlb_one(va); va += PAGE_SIZE; } - dsb(sy); /* Ensure completion of the TLB flush */ + dsb(ish); /* Ensure completion of the TLB flush */ isb(); }