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[50.57.142.19]) by mx.google.com with ESMTPS id sr19si1141134vcb.71.2014.04.03.02.01.25 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 03 Apr 2014 02:01:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVdV1-00057W-Qm; Thu, 03 Apr 2014 08:59:51 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WVdV0-00056w-5W for xen-devel@lists.xen.org; Thu, 03 Apr 2014 08:59:50 +0000 Received: from [193.109.254.147:38282] by server-7.bemta-14.messagelabs.com id 93/31-17726-5032D335; Thu, 03 Apr 2014 08:59:49 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1396515587!5961396!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 22862 invoked from network); 3 Apr 2014 08:59:48 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-14.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 3 Apr 2014 08:59:48 -0000 X-IronPort-AV: E=Sophos;i="4.97,785,1389744000"; d="scan'208";a="117591369" Received: from accessns.citrite.net (HELO FTLPEX01CL02.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 03 Apr 2014 08:59:47 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.79) with Microsoft SMTP Server id 14.2.342.4; Thu, 3 Apr 2014 04:59:46 -0400 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1WVdUw-0001BA-H3; Thu, 03 Apr 2014 08:59:46 +0000 From: Ian Campbell To: Date: Thu, 3 Apr 2014 09:59:45 +0100 Message-ID: <1396515585-5737-6-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1396515560.4211.33.camel@kazak.uk.xensource.com> References: <1396515560.4211.33.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH v4 6/6] xen: arm: relax barriers when flushing caches X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.181 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: We only need an inner shareable barrier here. Signed-off-by: Ian Campbell --- v4: new patch --- xen/include/asm-arm/page.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index a96e40b..b4d5597 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -263,20 +263,20 @@ extern size_t cacheline_bytes; static inline void clean_xen_dcache_va_range(void *p, unsigned long size) { void *end; - dsb(sy); /* So the CPU issues all writes to the range */ + dsb(ish); /* So the CPU issues all writes to the range */ for ( end = p + size; p < end; p += cacheline_bytes ) asm volatile (__clean_xen_dcache_one(0) : : "r" (p)); - dsb(sy); /* So we know the flushes happen before continuing */ + dsb(ish); /* So we know the flushes happen before continuing */ } static inline void clean_and_invalidate_xen_dcache_va_range (void *p, unsigned long size) { void *end; - dsb(sy); /* So the CPU issues all writes to the range */ + dsb(ish); /* So the CPU issues all writes to the range */ for ( end = p + size; p < end; p += cacheline_bytes ) asm volatile (__clean_and_invalidate_xen_dcache_one(0) : : "r" (p)); - dsb(sy); /* So we know the flushes happen before continuing */ + dsb(ish); /* So we know the flushes happen before continuing */ } /* Macros for flushing a single small item. The predicate is always @@ -288,9 +288,9 @@ static inline void clean_and_invalidate_xen_dcache_va_range clean_xen_dcache_va_range(_p, sizeof(x)); \ else \ asm volatile ( \ - "dsb sy;" /* Finish all earlier writes */ \ + "dsb ish;" /* Finish all earlier writes */ \ __clean_xen_dcache_one(0) \ - "dsb sy;" /* Finish flush before continuing */ \ + "dsb ish;" /* Finish flush before continuing */ \ : : "r" (_p), "m" (*_p)); \ } while (0) @@ -300,9 +300,9 @@ static inline void clean_and_invalidate_xen_dcache_va_range clean_and_invalidate_xen_dcache_va_range(_p, sizeof(x)); \ else \ asm volatile ( \ - "dsb sy;" /* Finish all earlier writes */ \ + "dsb ish;" /* Finish all earlier writes */ \ __clean_and_invalidate_xen_dcache_one(0) \ - "dsb sy;" /* Finish flush before continuing */ \ + "dsb ish;" /* Finish flush before continuing */ \ : : "r" (_p), "m" (*_p)); \ } while (0)