From patchwork Tue Apr 8 14:43:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 28001 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pd0-f199.google.com (mail-pd0-f199.google.com [209.85.192.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 98FD120447 for ; Tue, 8 Apr 2014 14:46:28 +0000 (UTC) Received: by mail-pd0-f199.google.com with SMTP id x10sf2916828pdj.6 for ; Tue, 08 Apr 2014 07:46:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:cc:subject:precedence:list-id:list-unsubscribe:list-post :list-help:list-subscribe:mime-version:sender:errors-to :x-original-sender:x-original-authentication-results:mailing-list :list-archive:content-type:content-transfer-encoding; bh=gakYxb5NCIIEAcTU3FOAjwpycpEjb7kTNWYUjyptRTE=; b=mnZ9c2WklVsjGXuzM55gv2unHtO3+fj7JqfSRrdGAdhhEikig/y96FDQYYjwCXz4Yw L9Kda5O22s1cZuzbzqL46t3iPklSyvQZK2cN5vNaWw0wV9/tNp54+1lClrfPuqZMyZ0M 1cTrJM4iMp+5RCPTdBuRK2h8qtfJAcgkQWuPs/NTJ1HS2AGfEG+vexvarvmoojBiknly ZmVbBJKvZPWZIoFsllSqv0BR5dTORhavkyyJX7hrvxq9qqh4+jJoEcc0208us6XxiOzd 4ztBua1dH8U+99zHBy9KaMczl0OFQ4JKeauBIoyKyBFBn22lD6aTesz2K8jLz+/phEDy BU6w== X-Gm-Message-State: ALoCoQmGimZpOLzo4+FsMI0j8FlENKE1gsHYk6H0HokmjWo3gOhuB6/xYiUqUcnfkokphF52pbc4 X-Received: by 10.66.233.65 with SMTP id tu1mr1582593pac.35.1396968387796; Tue, 08 Apr 2014 07:46:27 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.26.119 with SMTP id 110ls229928qgu.20.gmail; Tue, 08 Apr 2014 07:46:27 -0700 (PDT) X-Received: by 10.52.119.178 with SMTP id kv18mr343936vdb.39.1396968387620; Tue, 08 Apr 2014 07:46:27 -0700 (PDT) Received: from mail-vc0-f176.google.com (mail-vc0-f176.google.com [209.85.220.176]) by mx.google.com with ESMTPS id vd8si432774vdc.88.2014.04.08.07.46.27 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 08 Apr 2014 07:46:27 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.176; Received: by mail-vc0-f176.google.com with SMTP id lc6so834585vcb.7 for ; Tue, 08 Apr 2014 07:46:27 -0700 (PDT) X-Received: by 10.220.162.6 with SMTP id t6mr3649462vcx.12.1396968387545; Tue, 08 Apr 2014 07:46:27 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.12.8 with SMTP id v8csp251706vcv; Tue, 8 Apr 2014 07:46:27 -0700 (PDT) X-Received: by 10.220.133.80 with SMTP id e16mr3561661vct.13.1396968386917; Tue, 08 Apr 2014 07:46:26 -0700 (PDT) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id dy7si438568vec.18.2014.04.08.07.46.26 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 08 Apr 2014 07:46:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WXXG3-00008K-TB; Tue, 08 Apr 2014 14:44:15 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WXXG2-000085-54 for xen-devel@lists.xenproject.org; Tue, 08 Apr 2014 14:44:14 +0000 Received: from [85.158.137.68:48566] by server-17.bemta-3.messagelabs.com id 01/8D-22741-D3B04435; Tue, 08 Apr 2014 14:44:13 +0000 X-Env-Sender: julien.grall@linaro.org X-Msg-Ref: server-11.tower-31.messagelabs.com!1396968252!5739817!1 X-Originating-IP: [74.125.83.46] X-SpamReason: No, hits=0.0 required=7.0 tests= X-StarScan-Received: X-StarScan-Version: 6.11.1; banners=-,-,- X-VirusChecked: Checked Received: (qmail 2537 invoked from network); 8 Apr 2014 14:44:12 -0000 Received: from mail-ee0-f46.google.com (HELO mail-ee0-f46.google.com) (74.125.83.46) by server-11.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 8 Apr 2014 14:44:12 -0000 Received: by mail-ee0-f46.google.com with SMTP id t10so764730eei.5 for ; Tue, 08 Apr 2014 07:44:12 -0700 (PDT) X-Received: by 10.14.194.70 with SMTP id l46mr1207280een.95.1396968252165; Tue, 08 Apr 2014 07:44:12 -0700 (PDT) Received: from belegaer.uk.xensource.com ([185.25.64.249]) by mx.google.com with ESMTPSA id m42sm5031709eex.21.2014.04.08.07.44.11 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Apr 2014 07:44:11 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Tue, 8 Apr 2014 15:43:50 +0100 Message-Id: <1396968247-8768-2-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1396968247-8768-1-git-send-email-julien.grall@linaro.org> References: <1396968247-8768-1-git-send-email-julien.grall@linaro.org> Cc: stefano.stabellini@citrix.com, Julien Grall , tim@xen.org, ian.campbell@citrix.com Subject: [Xen-devel] [PATCH v3 01/18] xen/arm: timer: replace timer_dt_irq by timer_get_irq X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: The function is nearly only used to retrieve the IRQ number. There is one place where the IRQ type is used (in domain_build.c) but as the timer IRQ is virtualised for guest we might not have the same property (e.g active-low level sensitive interrupt). Replace timer_dt_irq by timer_get_irq which will return the IRQ number. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- Changes in v2: - Patch added --- xen/arch/arm/domain_build.c | 23 +++++++++++++---------- xen/arch/arm/time.c | 4 ++-- xen/arch/arm/vtimer.c | 4 ++-- xen/include/asm-arm/time.h | 4 ++-- 4 files changed, 19 insertions(+), 16 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 502db84..2035390 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -620,7 +620,7 @@ static int make_timer_node(const struct domain *d, void *fdt, u32 len; const void *compatible; int res; - const struct dt_irq *irq; + unsigned int irq; gic_interrupt_t intrs[3]; DPRINT("Create timer node\n"); @@ -647,17 +647,20 @@ static int make_timer_node(const struct domain *d, void *fdt, if ( res ) return res; - irq = timer_dt_irq(TIMER_PHYS_SECURE_PPI); - DPRINT(" Secure interrupt %u\n", irq->irq); - set_interrupt_ppi(intrs[0], irq->irq, 0xf, irq->type); + /* The timer IRQ is emulated by Xen. It always exposes an active-low + * level-sensitive interrupt */ - irq = timer_dt_irq(TIMER_PHYS_NONSECURE_PPI); - DPRINT(" Non secure interrupt %u\n", irq->irq); - set_interrupt_ppi(intrs[1], irq->irq, 0xf, irq->type); + irq = timer_get_irq(TIMER_PHYS_SECURE_PPI); + DPRINT(" Secure interrupt %u\n", irq); + set_interrupt_ppi(intrs[0], irq, 0xf, DT_IRQ_TYPE_LEVEL_LOW); - irq = timer_dt_irq(TIMER_VIRT_PPI); - DPRINT(" Virt interrupt %u\n", irq->irq); - set_interrupt_ppi(intrs[2], irq->irq, 0xf, irq->type); + irq = timer_get_irq(TIMER_PHYS_NONSECURE_PPI); + DPRINT(" Non secure interrupt %u\n", irq); + set_interrupt_ppi(intrs[1], irq, 0xf, DT_IRQ_TYPE_LEVEL_LOW); + + irq = timer_get_irq(TIMER_VIRT_PPI); + DPRINT(" Virt interrupt %u\n", irq); + set_interrupt_ppi(intrs[2], irq, 0xf, DT_IRQ_TYPE_LEVEL_LOW); res = fdt_property_interrupts(fdt, intrs, 3); if ( res ) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index 8a55016..2db6148 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -50,11 +50,11 @@ unsigned long __read_mostly cpu_khz; /* CPU clock frequency in kHz. */ static struct dt_irq timer_irq[MAX_TIMER_PPI]; -const struct dt_irq *timer_dt_irq(enum timer_ppi ppi) +unsigned int timer_get_irq(enum timer_ppi ppi) { ASSERT(ppi >= TIMER_PHYS_SECURE_PPI && ppi < MAX_TIMER_PPI); - return &timer_irq[ppi]; + return timer_irq[ppi].irq; } /*static inline*/ s_time_t ticks_to_ns(uint64_t ticks) diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index 5603702..4a944dcf 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -64,7 +64,7 @@ int vcpu_vtimer_init(struct vcpu *v) t->ctl = 0; t->cval = NOW(); t->irq = d0 - ? timer_dt_irq(TIMER_PHYS_NONSECURE_PPI)->irq + ? timer_get_irq(TIMER_PHYS_NONSECURE_PPI) : GUEST_TIMER_PHYS_NS_PPI; t->v = v; @@ -72,7 +72,7 @@ int vcpu_vtimer_init(struct vcpu *v) init_timer(&t->timer, virt_timer_expired, t, v->processor); t->ctl = 0; t->irq = d0 - ? timer_dt_irq(TIMER_VIRT_PPI)->irq + ? timer_get_irq(TIMER_VIRT_PPI) : GUEST_TIMER_VIRT_PPI; t->v = v; diff --git a/xen/include/asm-arm/time.h b/xen/include/asm-arm/time.h index d10c737..9bbab0b 100644 --- a/xen/include/asm-arm/time.h +++ b/xen/include/asm-arm/time.h @@ -22,8 +22,8 @@ enum timer_ppi MAX_TIMER_PPI = 4, }; -/* Get one of the timer IRQ description */ -const struct dt_irq* timer_dt_irq(enum timer_ppi ppi); +/* Get one of the timer IRQ number */ +unsigned int timer_get_irq(enum timer_ppi ppi); /* Route timer's IRQ on this CPU */ extern void __cpuinit route_timer_interrupt(void);